Lab Syllabus (tentative)

Fall 2008
Date	Lab Topic	Pre-lab due on Tuesdays of 1st lab session
Tue. Sept. 9 & Fr. Sept. 12	Lab 1: Overview of the Xilinx ISE8.2i tools Safety issues Full Adder Tutorials on Schematic, simulator and implementation with the ISE8.2i Xilinx Design System Note: Pre-Lab is due Tue Sept. 9 before 12pm.	Tue. Sept. 9
Sept. 16& 19	Lab 2: Four bit Adder Design and simulation of a 4-bit Adder VHDL HDL (Hardware description language) 7-segment decoder	Tue. Sept. 16
Sept. 23& 26	Lab 3: Carry Look-ahead Adder Delays in ripple carry and carry look-ahead adders Design of a 16-bit carry look-ahead adder Measuring delays in adders	Tue. Sept. 23
Sept. 30 & Oct.3	Lab 4 : Combinational Multiplier 4x4-bit multiplier Binary-to-BCD conversion Timing Constraints Reading ISE Reports	Tue. Sept 30 (2 weeks)
Oct. 7 & 10	Lab 4 continued.	Tue. Oct. 7
Oct. 14	Fall Break
Oct. 21 & 24	Lab 5 : Mini Project: ALU Design and Implementation Design a 8-bit ALU Use of the Core Generator Implementation and testing  the ALU	Tue. Oct. 21
Oct. 28 & 31	Lab 5: ALU continued (2nd week)
Nov. 4 & 7	Lab 7: Design and Implementation of a Digital Lock	Tue. Nov. 4
Nov. 11& 14	Lab 8 : Calculator	Tue. Nov. 11
Nov. 18 & 21 Dec. 2 & 5 [part 2].	Lab 9: Final Project: Electronic Dice Game Datapath and Control Unit Timing issues Lab report is due first day of finals Demo needs to be given not later than Monday Dec. 11th	Nov. 18. & Dec. 2 (2 weeks)

• Xilinx Resources
• Xilinx Answers
• Xilinx Support
• Xilinx: TechTips
• Xilinx: F2.1i manual
• Common mistakes
• Xilinx VHDL Reference Guide
• VHDL Language Guide

Supported by a grant of Xilinx Corporation 

Back to the ESE200 Homepage Created by Jan Van der Spiegel
Updated July 28, 2008.