Andrew D. Hilton

I finished my PhD at the University of Pennsylvania in summer of 2010, where I used to be a student in the Architecture and Compilers Group where I am advised by Amir Roth. I currently work at IBM in Research Triangle Park, North Carolina as part of the performance modelling and analysis team. Here is my (slightly out-of-date now) cv.

My primary research interest is in processor designs to provide high performance in an energy efficient way despite the relatively long latency of main memory. My work focuses on the use of speculative retirement—the ability to speculatively allow instructions to exit the pipeline when they would typically stall it. I have proposed two architectures, BOLT and iCFP which couple CFP-style re-execution of miss-dependent instructions with speculative retirement. My dissertation research will address the mechanisms for tracking speculatively retired loads and stores in such a context. In addition to my architecture research, I am currently collaborating with Jeff Vaughan on a security project called "Paladin: Helping Programs Help Themselves with System Call Interposition"

Dissertation:

Publications:

Teaching:

I was selected by the Center for Teaching and Learning as one of six recipients of their Graduate Fellowship for Teaching Excellence for 2008-09.

I taught the following classes:
I TAed the following classes:

Other:

My WPE-II exam was on Hardware for Exploiting Data Level Parallelism in Spring 2006.
This exam involves reading 3-4 papers on a topic, providing a written analysis, and giving a roughly 45 minute talk.

Before coming to Penn, I was an undergraduate and then Masters student at Georgia Tech. My advisor there was Olin Shivers.

Contact Info:

Department of CIS
Levine Hall
3330 Walnut Street
Philadelphia, PA 19104-6389

Email: a d h i l t o n @ c i s . u p e n n. e d u