Writings on Compute Models and Design Patterns

• Very Large Scale Spatial Computing (UMC 2002) -- why we need new models [Abstract and Pointers]
• SCORE -- a pipe-and-filter system architecture suitable for compute-centric tasks
  • Stream Computations Organized for Reconfigurable Execution (Journal of Microprocessors and Microsystems, 2006) -- description and tie to system architectures; most complete roundup of supporting work [Abstract and DOI Link]
  • Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial (full version web only; short version FPL 2000) -- initial description and most comprehensive single introduction [Abstract and Pointers]
  • Analysis of Quasi-Static Scheduling Techniques in a Virtualized Reconfigurable Machine (FPGA 2002) -- demonstrates that we can efficiently schedule SCORE computations using a quasistatic approach with modest run-time overhead [Abstract and Pointers]
  • additional links
  • VLIW-SCORE: Beyond C for Sequential Control of SPICE FPGA Acceleration (ICFPT 2011) -- shows use of SCORE for integrating larger computation and coordinating ``control'' portion [Abstract and Paper Link]
• GraphStep -- an actor-oriented system architecture suitable for data-centric and graph processing tasks
  • Spatial hardware implementation for sparse graph algorithms in GraphStep (ACM TAAS 2011) -- motivation, overview, and demonstratin of basic benefits [Abstract and Paper Link]
  • Floating-Point Sparse-Matrix Vector Multiply for FPGAs (FPGA 2005) -- sample application which fits into the GraphStep model; shows that vintage 2004 FPGAs sustain higher double-precision floating point performance per component (e.g. FPGA, processor) than the best microprocessors, especially when scaling to tens of components [Abstract and Paper Links]
  • Stochastic Spatial Routing for Reconfigurable Networks (Journal of Microprocessors and Microsystems, 2006) -- how can we exploit parallelism to accellerate routing? (can be thought as a pre-GraphStep application example/motivator) This is a complete, stand-alone description and contains more detailed experiments and evaluation than earlier conference papers (below) [Abstract and DOI Link]
  • Hardware-Assisted Simulated Annealing with Application for Fast FPGA Placement (FPGA 2003) -- how to use a collection of FPGAs to place an FPGA ; or how to use a ``paged'' device to place problems for itself. (can be thought as a pre-GraphStep application example/motivator; this particular formulation uses a Cellular Automata system architecture, but the idea can be adapted, especially to reduce the area required to solve large problems) [Abstract and Paper Link]
  • Hardware-Assisted Fast Routing (FCCM 2002) -- first description of how to design devices for self routing [Abstract andPaper Link]
  • Stochastic, Spatial Routing for Hypergraphs, Trees, and Meshes (FPGA 2003) -- closing the quality gap and expanding the realm of applicability for self routing (largely superceded by JMM article above) [Abstract and Paper Link]
  • SPICE²: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA (IEEE TRCAD 2012) -- SPICE includes two distinct components---model-evaluation and matrix-solve---that are different kinds of irregular graph problems; it also includes an control piece [Abstract and Paper Link]
• Design Patterns -- component solutions to recurring problems in the design of reconfigurable applications
  • Designs Patterns for Reconfigurable Computing (FCCM 2004) -- introduction of idea, samples, and initial catalog [Abstract and Paper Links]