Reconfigurable Computing/FPGA Papers (and Molecular Electronics)

FPT2023

Dongjoon Park, Zhijing Yao, Yuanlong Xiao, and André DeHon. Asymmetry in Butterfly Fat Tree FPGA NoC. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2023. [Abstract and Paper Link]

TRETS2023

Yuanlong Xiao, Dongjoon Park, Zeyu Jason Niu, Aditya Hota and André DeHon. ExHiPR: Extended High-level Partial Reconfiguration for Fast Incremental FPGA Compilation. In ACM Transactions on Reconfigurable Technology and Systems (TRETS), DOI: 10.1145/3617837, September, 2023. [Abstract and Paper Link]

FPT2022

Dongjoon Park, Yuanlong Xiao, and André DeHon. Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2022. [Abstract and Paper Link]

FPL2022

Yuanlong Xiao, Aditya Hota, Dongjoon Park, and André DeHon. HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation. In Proceedings of the International Conference on Field Programmable Logic and Applications, August, 2022. [Abstract and Paper Link]

ASPLOS2022

Yuanlong Xiao, Eric Micallef, Andrew Butt, Matthew Hofmann, Marc Alston, Matthew Goldsmith, Andrew Merczynski-Hait and André DeHon. PLD: Fast FPGA Compilation to Make Reconfigurable Acceleration Compatible with Modern Incremental Refinement Software Development. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems, March, 2022. [Abstract and Paper Link]

JETC2022

Nicholas Roessler and André DeHon. SCALPEL: Exploring the Limits of Tag-Enforced Compartmentalization. In ACM Journal on Emerging Technologies in Computing Systems, Volume 18, Number 1, January, 2022. [Abstract and Paper Link]

CCS2021

Nikos Vasilakis, Cristian-Alexandru Staicu, Gigoris Ntousakis, Konstantinos Kallas, Ben Karel, André DeHon, and Michael Pradel. Preventing Dynamic Library Compromise on Node.js via RWX-Based Privilege Reduction. In Proceedings of the ACM SIGSAC Conference on Computer and Communications Security, November, 2021. [Abstract and Paper Link]

RAID2021

Nicholas Roessler, Lucas Atayde, Imani Palmer, Derrick McKee, Jai Pandey, Vasileios P. Kemerlis, Mathias Payer, Adam Bates, André DeHon, Jonthan M. Smith, and Nathan Dauhtenhahn. μSCOPE: A Methodology for Analyzing Least-Privilege Compartmentalization in Large Software Artifacts. In Proceedings of the International Symposium on Research in Attacks, Intrusions and Defenses, pages 296--311, October, 2021. [Abstract and Paper Link]

FCCM2021a

Matthew Hofmann, Zhiyao Tang, Jonathan Orgill, Jonathan Nelson, David Glanzman, Brent Nelson, and André DeHon. XBERT: Xilinx Logical-Level Bitstream Embedded RAM Transfusion. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, May, 2021. [Abstract and Paper Link]

FCCM2021b

Eric Micallef, Yuanlong Xiao, and André DeHon. HLS-Compatible, Embedded-Processor Stream Links. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, May, 2021. [Abstract and Paper Link]

NSDI2021

Nik Sultana, John Sonchack, Isaac Pedisich, Hans Giesen, Zhaoyang Han, Nishanth Shyamkumar, Shivani Burad, André DeHon, and Boon Thau Loo. Flightplan: Dataplane Disaggregation and Placement for P4 Programs. In USENIX Symposium on Network Systems Design and Implementation, April, 2021. [Abstract and Paper Link]

FPT2020

Yuanlong Xiao, Syed Tousif Ahmed, and André DeHon. Fast Linking of Separately-Compiled FPGA Blocks without a NoC. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2020. [Abstract and Paper Link]

CoNEXT2020

Joel Hypolite, John Sonchack, Shlomo Hershkop, Nathan Dautenhahn, André DeHon, and Jonathan M. Smith. DeepMatch: Practical Deep Packet Inspection in the Data Plane using Network Processors. In Proceedings of the International Conference on emerging Networking EXperiments and Technologies, December, 2020. [Abstract and Paper Link]

FPT2019b

Yuanlong Xiao, Dongjoon Park, Andrew Butt, Hans Giesen, Zhaoyang Han, Rui Ding, Nevo Magnezi, Raphael Rubin, and André DeHon. Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2019. [Abstract and Paper Link]

FPT2019a

Vipula Sateesh, Connor Mkckeon, Jared Winograd, and André DeHon. Pipelined Parallel Finite Automata Evaluation. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2019. [Abstract and Paper Link]

NETCOMPUTE2018

Hans Giesen, Anirudh Chelluri, Lei Shi, Nishanth Prabhu, Anthony J. McAuley, John Sonchack, Nik Sultana, Alexander Poylisher, Latha Kant, André DeHon, and Boon Thau Loo. In-network Computing to the Rescue of Faulty Links. in Proceedings of the ACM SIGCOMM Workshop on In-Network Computing, August, 2018. [Abstract and Paper Link]

IEEESP2018

Nick Roessler and André DeHon. Protecting the Stack with Metadata Policies and Tagged Hardware. In IEEE Symposium on Security and Privacy, May, 2018. [Abstract and Paper Link]

TRETS2018

Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim and André DeHon. Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). In ACM Transactions on Reconfigurable Technology and Systems (TRETS) , Volume 11, Number 1, Article No. 3, DOI: 10.1145/3158229, January, 2018. [Abstract and Paper Link]

NDSS2018

Nikos Vasilakis, Ben Karel, Nick Roessler, Nathan Dautenhahn, André DeHon, and Jonathan M. Smith. BreakApp: Automated, Flexible Application Compartmentalization. In Proceedings of the Network and Distributed System Security Symposium, February, 2018. [Abstract and Paper Link]

IEEEDT2017

Hans Giesen, Raphael Rubin, Benjamin Gojman, and André DeHon. Self-Adaptive Timing Repair. In IEEE Design and Test of Computers, Volume 34, Number 6, Pages 54--62, November-December, 2017. [Abstract and IEEE Xplorer Link]

FPGA2017

Hans Giesen, Raphael Rubin, Benjamin Gojman, and André DeHon. Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays. In Proceedings of the International Symposium on Field Programmable Gate Arrays, February, 2017. [Abstract and Paper Link]

TRETS2016

Edin Kadric, David Lakata, and André DeHon. Impact of Parallelism and Memory Architecture on FPGA Energy Consumption. In ACM Transactions on Reconfigurable Technology and Systems (TRETS) , Volume 9, Number 4, Article No. 30, DOI: 10.1145/2857057, August, 2016. [Abstract and Paper Link]

FCCM2016

Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim and André DeHon. Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-reconfiguration (COSMIC TRIP) In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, May, 2016. [Abstract and Paper Link]

TC2016

Edin Kadric, Paul Gurniak, and André DeHon. Accurate Parallel Floating-Point Accumulation. In IEEE Transactions on Computers, Volume 65, Number 11, pp. 3224--3238, November 2016. [Abstract and Paper Link]

FPGA2016

Timothy A. Linscott, Benjamin Gojman, Raphael Rubin, and André DeHon. Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement. In Proceedings of the International Symposium on Field Programmable Gate Arrays, February, 2016. [Abstract and Paper Link]

FPT2015

Hyunseok Park, Shreel Vijayvargiya, André DeHon. Energy Minimization in the Time-Space Continuum. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2015. [Abstract and Paper Link]

PROCIEEE2015A

André DeHon. Fundamental Underpinnings of Reconfigurable Computing Architectures. In Proc. of the IEEE (Special Issue on Reconfigurable Sysems), Volume 103, Number 3, pp. 355--378, DOI: 10.1109/JPROC.2014.2386883, March, 2015. [Abstract and Paper Link]

PROCIEEE2015B

Russell Tessier, Kenneth Pocek, and André DeHon. Reconfigurable Computing Architectures. In Proc. of the IEEE (Special Issue on Reconfigurable Sysems), Volume 103, Number 3, pp. 332--354, DOI: 10.1109/JPROC.2014.2386883, March, 2015. [Abstract and Paper Link]

ASPLOS2015

Udit Dhawan, Catalin Hritcu, Nikos Vasilakis, Raphael Rubin, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight, Jr., Benjamin C. Pierce, and André DeHon. Architectural Support for Software-Defined Metadata Processing. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems, March, 2015. [Abstract and Paper Link]

FPGA2015

Edin Kadric, David Lakata, and André DeHon. Impact of Memory Architecture on FPGA Energy Consumption. In Proceedings of the International Symposium on Field Programmable Gate Arrays, February, 2015. [Abstract and Paper Link]

TRETS2015

Udit Dhawan and André DeHon. Area-Efficient Near-Associative Memories on FPGAs. In ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 7, Number 4, DOI: 10.1145/2629471, January, 2015. [Abstract and Paper Link]

TRETS2014

Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, and André DeHon. GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays using Timing Extraction. In ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 7, Number 4, DOI: 10.1145/2597889, December, 2014. [Abstract and Paper Link]

FPT2014

Albert Kwon, Kaiyu Zhang, Perk Lun Lim, Yuchen Pan, Jonathan M. Smith, and André DeHon. RotoRouter: Router Support for Endpoint-Authorized Decentralized Traffic Filtering to Prevent DoS Attacks. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2014. [Abstract and Paper Link]

HASP2014

Udit Dhawan, Nikos Vasilakis, Raphael Rubin, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight, Jr., Benjamin C. Pierce, andAndré DeHon. PUMP: A Programmable Unit for Metadata Processing. In Proceedings of the 3rd International Workshop on Hardware and Architectural Support for Security and Privacy, June, 2014. [Abstract and Paper Link]

FCCM2014c

Edin Kadric, Kunal Mahajan, and André DeHon. Kung Fu Data Energy---Minimizing Communication Energy in FPGA Computations. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, May, 2014. [Abstract and Paper Link]

FCCM2014b

Edin Kadric, Kunal Mahajan, and André DeHon. Energy Reduction through Differential Reliability and Lightweight Checking. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, May, 2014. [Abstract and Paper Link]

FCCM2014a

Benjamin Gojman and André DeHon. GROK-INT: Generating Real On-chip Knowledge for Interconnect Delays Using Timing Extraction. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, May, 2014. [Abstract and Paper Link]

FPGA2014

André DeHon. Wordwidth, Instructions, Looping, and Virtualization---The Role of Sharing in Absolute Energy Minimization. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 189--198, February, 2014. [Abstract and Paper Link]

POPL2014

Arthur Azevedo de Amorim, Nathan Collins, André DeHon, Delphine Demange, Cătălin Hriţcu, David Pichardie, Benjamin C. Pierce, Randy Pollack, Andrew Tolmach. A Verified Information-Flow Architecture. In Proceedings of the ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, January 2014. [Abstract and Paper Link]

FPT2013

André DeHon and Nikil Mehta. Exploiting Partially Defective LUTs: Why You Don't Need Perfect Fabrication. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2013. [Abstract and Paper Link]

CCS2013

Albert Kwon, Udit Dhawan, Jonathan M. Smith, Thomas F. Knight, Jr. and André DeHon. Low-Fat Pointers: Compact Encoding and Efficient Gate-Level Implementation of Fat Pointers for Spatial Safety and Capability-based Security. In Proceedings of the ACM Conference on Computer and Communications Security, November, 2013. [Abstract and Paper Link]

ARITH2013

Edin Kadric, Paul Gurniak, and André DeHon. Accurate Parallel Floating-Point Accumulation. In Proceedings of the IEEE Symposium on Computer Arithmetic, April, 2013. [Abstract and Paper Link]

FPGA2013a

Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, and André DeHon. GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays using Timing Extraction. In Proceedings of the International Symposium on Field Programmable Gate Arrays, February, 2013. [Abstract and Paper Link]

FPGA2013b

Udit Dhawan and André DeHon. Area-Efficient Near-Associative Memories on FPGAs. In Proceedings of the International Symposium on Field Programmable Gate Arrays, February, 2013. [Abstract and Paper Link]

FPGA2013c

André DeHon. Location, Location, Location---The Role of Spatial Locality in Asymptotic Energy Minimization. In Proceedings of the International Symposium on Field Programmable Gate Arrays, February, 2013. [Abstract and Paper Link]

FPT2012

Yutian Huan and André DeHon. FPGA Optimized Packet-Switched NoC using Split and Merge Primitives. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2012. [Abstract and Paper Link]

AHNS2012

Udit Dhawan, Albert Kwon, Edin Kadric, Catalin Hritcu, Benjamin C. Pierce, Jonathan M. Smith, Gregory Malecha, Greg Morrisett, Thomas F. Knight, Jr., Andrew Sutherland, Tom Hawkins, Amanda Zyxnfryx, David Wittenberg, Peter Trei, Sumit Ray, Greg Sullivan, André DeHon. Hardware Support for Safety Interlocks and Introspection. In Proceedings of the SASO Workshop on Adaptive Host and Network Security, September 14, 2012. [Abstract and Paper Link]

FPGA2012

Nikil Mehta and André DeHon. Limit Study of Energy & Delay Benefits of Component-Specific Routing. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 97--106, February, 2012. [Abstract and Paper Link]

TRCAD2012

Nachiket Kapre and André DeHon. SPICE²: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 31, Number 1, pp. 9--12, DOI: 10.1109/TCAD.2011.2173199, January, 2012. [Abstract and Paper Link]

TRETS2011

Raphael Rubin and André DeHon. Choose-Your-Own-Adventure Routing: Lightweight Load-Time Defect Avoidance. In ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 4, Number 4, DOI: 10.1145/2068716.2068719, December, 2011. [Abstract and Paper Link]

FPT2011

Nachiket Kapre and André DeHon. VLIW-SCORE: Beyond C for Sequential Control of SPICE FPGA Acceleration. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2011. [Abstract and Paper Link]

TAAS2011

Michael deLorimier, Nachiket Kapre, Nikil Mehta, and André DeHon. Spatial hardware implementation for sparse graph algorithms in GraphStep. In ACM Transactions on Autonomous and Adaptive Systems (TAAS), Volume 6, Number 3, DOI: 10.1145/2019583.2019584, September, 2011. [Abstract and Paper Link]

IJRC2011

Nachiket Kapre and André DeHon. An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads. In International Journal of Reconfigurable Computing, Volume 2011, Article ID 745147, DOI: 10.1155/2011/745147, March, 2011. [Abstract and Paper Link]

FPGA2011

Raphael Rubin and André DeHon. Timing-Driven Pathfinder Pathology and Remediation: Quantifying and Reducing Delay Noise in VPR-Pathfinder. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 173--176, February, 2011. [Abstract and Paper Link]

Computer2011

André DeHon and Benjamin Gojman. Crystals and Snowflakes: Building Computation from Nanowire Crossbars In IEEE Computer, Volume 44, Number 2, pp. 37--45, February, 2011. [Abstract and Paper Links]

RECOSOC2010

Nachiket Kapre and André DeHon. An NoC Traffic Compiler for efficient FPGA implementation of Parallel Graph Applications. In Proceedings of the Workshop on Reconfigurable Communication-Centric Systems on Chip, May, 2010. [Abstract and Paper Links]

IETCDT2009

Benjamin Gojman, Harika Manem, Garret S. Rose, and André DeHon. Inversion Schemes for Sublithographic Programmable Logic Arrays. In IET Computers and Digital Techniques, Volume 3, Number 6, Pages 525--642, November, 2009. [Abstract and IEEE link].

FPT2009a

Benjamin Gojman and André DeHon. VMATCH: Using Logical Variation to Counteract Physical Variation in Bottom-Up, Nanoscale Systems. In Proceedings of the IEEE International Conference on Field-Programmable Technology, pages 78--87, December, 2009. [Abstract and Paper Links]

FPT2009b

Nachiket Kapre and André DeHon. Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs. In Proceedings of the IEEE International Conference on Field-Programmable Technology, pages 190--198, December, 2009. [Abstract and Paper Links]

FPL2009

Nachiket Kapre and André DeHon. Performance Comparison of Single-Precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core Processors. In Proceedings of the International Conference on Field Programmable Logic and Applications, pages 65--27, September, 2009. [Abstract and Paper Links]

FCCM2009

Nachiket Kapre and André DeHon. Accelerating SPICE Model-Evaluation using FPGAs. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pages 37--44, April 2009. [Abstract and Paper Links]

TRVLSI2009

Helia Naeimi and André DeHon. Fault Secure Encoder and Decoder for NanoMemory Applications. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 17, Number 4, Pages 473--486, April 2009. [Abstract and IEEE link].

FPGA2009

Raphael Rubin and André DeHon. Choose-Your-Own-Adventure Routing: Lightweight Load-Time Defect Avoidance. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 23--32, February, 2009. [Abstract and Paper Link]

TC2009

Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, and André DeHon. Pipelining Saturated Accumulation. In IEEE Transactions on Computers, Volume 58, Number 2, pp. 208--219, February, 2009. [Abstract and Paper Link]

NDCS2008

André DeHon. The Case for Reconfigurable Components with Logic Scrubbing: Regular Hygiene Keeps Logic FIT (low). In Proceedings of the IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems (NDCS2008), September 2008. [Abstract and Paper Links]

NANOTECHNOLOGY2008

Helia Naeimi and André DeHon. Fault-Tolerant Sub-lithographic Design with Rollback Recovery. In Nanotechnology, Volume 19, Number 11, Article 115708, March 19, 2008. [Abstract and Paper Links]

NANONETS2007

Helia Naeimi and André DeHon. Fault Tolerant Nano-Memory with Fault Secure Encoder and Decoder. In Proceedings of the International Conference on Nano-Networks (Nanonets2007), September 2007. [Abstract and Paper Links]

DFT2007

Helia Naeimi and André DeHon. Fault Secure Encoder and Decoder for Memory Applications. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS2007), September 2007. [Abstract and Paper Links]

ARITH2007

Nachiket Kapre and André DeHon. Optimistic Parallelization of Floating-Point Accumulation. In Proceedings of the IEEE Symposium on Computer Arithmetic (ARITH18), pp. 205--213, June 2007. [Abstract and Paper Links]

NANONETS2006b

Benjamin Gojman, Raphael Rubin, Concetta Pilotto, Tetsufumi Tanamoto, and André DeHon. 3D Nanowire-Based Programmable Logic. In Proceedings of the International Conference on Nano-Networks (Nanonets2006), September 2006. [Abstract and Paper Links]

NANONETS2006a

Kumiko Numora, Keiko Abe, Shinobu Fujita, and André DeHon. Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices. In Proceedings of the International Conference on Nano-Networks (Nanonets2006), September 2006. [Abstract and Paper Links]

JETC2006

John E. Savage, Eric Rachlin, André DeHon, Charles M. Lieber, and Yue Wu. Radial Addressing of Nanowires. In ACM Journal on Emerging Technologies in Computing Systems, Volume 2, Number 2, Pages 129--154, April 2006. [Abstract and ACM Link].

JMM2006a

André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, and John Wawrzynek. Stream Computations Organized for Reconfigurable Execution. In Journal of Microprocessors and Microsystems, Volume 30, Number 6, Pages 334--354, September, 2006. [Abstract and DOI Link]

JMM2006b

André DeHon, Randy Huang, and John Wawrzynek. Stochastic Spatial Routing for Reconfigurable Networks. In Journal of Microprocessors and Microsystems, Volume 30, Number 6, Pages 301--318, September, 2006. [Abstract and DOI Link]

FCCM2006a

Michael deLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomas Uribe, Thomas F. Knight, Jr. and André DeHon. GraphStep: A System Architecture for Sparse-Graph Algorithms. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 2006. [Abstract and Paper Links]

FCCM2006b

Nachiket Kapre, Nikil Mehta, Michael deLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael Wrighton, and André DeHon. Packet-Switched vs. Time-Multiplexed FPGA Overlay Networks. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 2006. [Abstract and Paper Links]

ASPDAC2006

Michael Wrighton and André DeHon. SAT-Based Optimal Hypergraph Partitioning with Replication. In Proceedings of the Asia and South Pacific Design Automation Conference, January 2006. [Abstract and paper links].

ICFPT2005

Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, and André DeHon. Pipelining Saturated Accumulation. In Proceedings of the International Conference on Field-Programmable Technology, December, 2005. [Abstract and paper links].

TNANO2005b

André DeHon. Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches. In IEEE Transactions on Nanotechnology, Volume 4, Number 6, Pages 681--687, Nov. 2005. [Abstract and IEEE link].

JETC2005

André DeHon. Nanowire-Based Programmable Architectures. In ACM Journal on Emerging Technologies in Computing Systems, Volume 1, Number 2, Pages 109--162, July 2005. [Abstract and ACM Link].

IEEEDT2005

André DeHon and Helia Naeimi. Seven Strategies for Tolerating Highly Defective Fabrication. In IEEE Design and Test of Computers, Volume 22, Number 4, Pages 306--315, July-August 2005. [Abstract and IEEE link].

TNANO2005a

André DeHon, Seth Copen Goldstein, Philip J. Kuekes, and Patrick Lincoln. Non-Photolithographic Nanoscale Memory Density Prospects. In IEEE Transactions on Nanotechnology, Volume 4, Number 2, Pages 215--228, March 2005. [Abstract and IEEE link].

FPGA2005a

André DeHon. Design of Programmable Interconnect for Sublithographic Programmable Logic Arrays. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 127--137,February, 2005. [Abstract, paper, and slide links].

FPGA2005b

Michael deLorimier and André DeHon. Floating-Point Sparse Matrix-Vector Multiply for FPGAs. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 75--85, February, 2005. [Abstract, paper, and slide links].

ICFPT2004

Helia Naeimi and André DeHon. A Greedy Algorithm for Tolerating Defective Crosspoints in NanoPLA Design. In Proceedings of the International Conference on Field-Programmable Technology, pages 49--56, December, 2004. [Abstract and paper links].

TRVLSI2004a

André DeHon and Raphael Rubin. Design of FPGA Interconnect for Multilevel Metalization. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 12, Number 10, Pages 1038--1050, October 2004. [Abstract and IEEE link].

TRVLSI2004b

André DeHon. Unifying Mesh- and Tree-Based Programmable Interconnect In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 12, Number 10, Pages 1051--1065, October 2004. [Abstract and IEEE link].

LLNSD2004

André DeHon. Law of Large Numbers System Design. In Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, pp. 213--241, Kluwer, 2004. [Abstract].

FCCM2004

André DeHon, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda, Helia Naeimi, Michael Vanier, and Michael Wrighton. Design Patterns for Reconfigurable Computing. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 2004. [Abstract and paper link].

FPGA2004

André DeHon and Michael J. Wilson. Nanowire-Based Sublithographic Programmable Logic Arrays. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 123--132, February, 2004. [Abstract, paper, and slide links].

TNANO2003

André DeHon, Patrick Lincoln, and John E. Savage. Stochastic Assembly of Sublithographic Nanoscale Interfaces. In IEEE Transactions on Nanotechnology, Volume 2, Number 3, Pages 165--174, September 2003. [Abstract and IEEE link].

HOTCHIPS2003

André DeHon with Charles M. Lieber, Patrick Lincoln, and John E. Savage. Sub-lithographic Semiconductor Computing Systems. In Hot Chips Symposium 2003, August 17--19, 2003. [Abstract, paper, slides].

TNANO2003

André DeHon. Array-Based Architecture for FET-Based, Nanoscale Electronics. In IEEE Transactions on Nanotechnology, Volume 2, Number 1, Pages 23--32, Mar 2003. [Abstract and IEEE link].

FPGA2003a

Raphael Rubin and André DeHon. Design of FPGA Interconnect for Multilevel Metalization. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 154--163, February, 2003. [Abstract, paper, and slide links].

FPGA2003b

Michael Wrighton and André DeHon. Hardware-Assisted Simulated Annealing with Application for Fast FPGA Placement. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 33--42, February, 2003. [Abstract, paper, and slide links].

FPGA2003c

Randy Huang, John Wawrzynek, and André DeHon. Stochastic, Spatial Routing for Hypergraphs, Trees, and Meshes. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 78--87, February, 2003. [Abstract, paper, and slide links].

ICCAD2002

Michael Butts, André DeHon, and Seth Copen Goldstein, Molecular Electronics: Devices, Systems and Tools for Gigagate, Gigabit Chips. In Proceedings of the International Conference on Computer-Aided Design, pages 433--440, November, 2002. [Abstract, paper, and slide links].

UMC2002

André DeHon. Very Large Scale Spatial Computing. In Proceedings of the Third International Conference on Unconventional Models of Computation, pages 27--37, October 2002. [Abstract, paper, and slide links].

FCCM2002

André DeHon, Randy Huang, and John Wawrzynek. Hardware-Assisted Fast Routing. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pages 205--215, April 2002. [Abstract, paper, and slide links].

NSC2002

André DeHon. Array-Based Architecture for Molecular Electronics. In Proceedings of the First Workshop on Non-Silicon Computation, February 2002. [Abstract, paper, and slide links].

FPGA2002

Yury Markovskiy, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, and André DeHon. Analysis of QuasiStatic Scheduling Techniques in a Virtualized Reconfigurable Machine. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 196--205, February 2002. [Abstract, paper, and slide links].

MSP2001

Eylon Caspi, Randy Huang, Yury Markovskiy, Joseph Yeh, John Wawrzynek, and André DeHon. A Streaming Multi-Threaded Model. In Third Workshop on Media and Stream Processing (MSP-3), December 2, 2001, [Abstract, paper links].

SLIP2001

André DeHon. Rent's Rule Based Switching Requirements. In System-Level Interconnect Prediction (SLIP 2001), pages 197--204, March 31--April 1, 2001, [Abstract, paper links].

FPL2000

Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, and André DeHon. Stream Computations Organized for Reconfigurable Execution (SCORE): Extended Abstract. In Conference on Field Programmable Logic and Applications (FPL '2000), pages 605--614, August 28--30, 2000. [Abstract, paper links].

SPAA2000

André DeHon. Compact, Multilayer Layout for Butterfly Fat-Tree. In Twelfth Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA 2000), pages 206--215, July 9-12, 2000. [Abstract, paper links].

Computer2000

André DeHon. The Density Advantage of Configurable Computing. IEEE Computer, 33(4):41--49, April 2000. [Abstract and paper link]

DAC99

André DeHon, John Wawrzynek. Reconfigurable Computing: What, Why, and Design Automation Requirements? In Proceedings of the 1999 Design Automation Conference, pages 610--615, June 1999. [Abstract, paper, and slide links].

VLSI99

Stylianos Perissakis, Yangsung Joo, Jinhong Ahn, André DeHon, and John Wawrzynek. Embedded DRAM for a Reconfigurable Array. In Proceedings of the 1999 Symposium on VLSI Circuits, June 1999. [Abstract, paper, and slide links].

FPGA99a

André DeHon. Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why you don't really want 100% LUT utilization). In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 125--134, February 1999. [Abstract, paper, and slide links].

FPGA99b

William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, Varghese George, John Wawrzynek, André DeHon. HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 69--78, February 1999. [Abstract, paper, and slide links].

ISSCC99

Andre DeHon, Trends toward Spatial Computing Architectures. In ISSCC Digest of Technical Papers, pages 362--363. IEEE, February 1999. [Abstract, paper, and slide links].

SPIE98

André DeHon. Comparing Computing Machines. In Configurable Computing: Technology and Applications, Proceedings of SPIE 3526, p. 124, November 1998. [Abstract, paper, and slide links]

FCCM98

Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, and John Wawrzynek. Object Oriented Circuit-Generators in Java. In Proceedings of the IEEE Symposium on Field-Programmable Gate Arrays for Custom Computing Machines. IEEE, IEEE, April 1998. [Abstract and paper links]

FPGA98

Timothy Callahan, Philip Chong, André DeHon, and John Wawrzynek. Fast Module Mapping and Placement for Datapaths in FPGAs. In Proceedings of the International Symposium on Field Programmable Gate Arrays, February 1998. [Abstract and paper].

HICSS97

William H. Mangione-Smith, Brad Hutchings, David Andrews, André DeHon, Carl Ebeling, Reiner Hartenstein, Oskar Mencer, John Morris, Krishna Palem, Viktor K. Prasanna, and Henk A. E. Spaanenburg. Seeking Solutions in Configurable Computing. IEEE Computer, 30(12):38--43, December 1997. [IEEE Xplore Link]

HC97

Ethan Mirsky and André DeHon. MATRIX: A Reconfigurable Computing Device with Configurable Instruction Distribution and Deployable Resources. In Hot Chips Symposium 1997, 1997. [Abstract, paper, and slides links].

FPD96

André DeHon. Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density. In Proceedings of the Fourth Canadian Workshop on Field-Programmable Devices, pages 47-54, May 1996. [Abstract, paper, and slide links].

FCCM96

Ethan Mirsky and Andre DeHon. MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, April 1996. [Abstract, paper, and slide links].

FPGA96a

Andre DeHon. DPGA Utilization and Application. In Proceedings of the 1996 International Symposium on Field Programmable Gate Arrays. ACM/SIGDA, February 1996. [Abstract, paper, and slide links].

FPGA96b

Andre DeHon. Entropy, Counting, and Programmable Interconnect. In Proceedings of the 1996 International Symposium on Field Programmable Gate Arrays. ACM/SIGDA, February 1996. [Abstract, paper, and slide links].

FPD95

Edward Tau, Ian Eslick, Derrick Chen, Jeremy Brown, and Andre DeHon. A First Generation DPGA Implementation. In Proceedings of the Third Canadian Workshop on Field-Programmable Devices, pages 138-143, May 1995. [Abstract, paper, slides link].

FCCM94

Andre DeHon. DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, April 1994. [Abstract, paper link].

FPGA94

Michael Bolotski, Andre DeHon, and Thomas F. Knight, Jr. Unifying FPGAs and SIMD Arrays. In FPGA Workshop, 1994. proceedings not available outside of the workshop [Abstract, paper, slide links].

Multiprocessor Interconnect Papers

VLSIDESIGN98

André DeHon and Thomas F. Knight Jr. High Performance Point-to-Point Transmission Line Signaling. VLSI Design, 7(1):111--129, 1998. [PDF] [PS]

IJHSES95

André DeHon, Fred Drenckhahn, Thomas F Knight Jr., and Henry Minsky. Three-Dimensional Packaging for High-Performance Interconnect in Large-Scale VLSI Systems. International Journal of High Speed Electronics and Systems, 6(4):613--630, 1995.

ITC94

Andre DeHon. In-System Timing Extraction and Control through Scan-Based, Test-Access Ports. In Proceedings of the International Test Conference, pages 350-359, 205 Tennyson Avenue, Suite C, Altoona, PA 16602, October 1994. IEEE, International Test Conference. [IEEE Xplore Link] [PS link].

ISCA94

Andre DeHon, Frederic Chong, Matthew Becker, Eran Egozy, Henry Minsky, Samuel Peretz, and Thomas F. Knight, Jr. METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks. In Proceedings of the International Symposium on Computer Architecture, pages 266-277, May 1994. [Abstract, paper links].

ISSCC93

Andre DeHon, Thomas F. Knight Jr., and Thomas Simon. Automatic Impedance Control. In ISSCC Digest of Technical Papers, pages 164-165. IEEE, February 1993. [IEEE Xplore Link] [PS link].

DFT92

Andre DeHon. Scan-Based Testability for Fault-tolerant Architectures. In Duncan M. Walker and Fabrizio Lombardi, editors, Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, pages 90-99. IEEE, IEEE Computer Society Press, 1992. [PDF] [PS]

ARVLSI92

Frederic Chong, Eran Egozy, and Andre DeHon. Fault Tolerance and Performance of Multipath Multistage Interconnection Networks. In Thomas F. Knight Jr. and John Savage, editors, Advanced Research in VLSI and Parallel Systems 1992, pages 227-242. MIT Press, March 1992. [PDF] [PS]

ISSMM91

Andre DeHon, Thomas F. Knight Jr., and Henry Minsky. Fault-Tolerant Design for Multistage Routing Networks. In International Symposium on Shared Memory Multiprocessing, pages 60-71. Information Processing Society of Japan, April 1991. [PDF (having problems with)] [PS]

HotChips91

Henry Minsky, Andre DeHon, and Thomas F. Knight Jr. RN1: Low-Latency, Dilated, Crossbar Router. In Hot Chips Symposium III, 1991. [PDF].

ARVLSI91

Andre DeHon. Practical Schemes for Fat-Tree Network Construction. In Carlo H. Sequin, editor, Advanced Research in VLSI: International Conference 1991, pages 307-322. MIT Press, March 1991. [PDF] [PS]