Writings on Sublithographic/Molecular-Scale Architecture

• Nanowire-Based Programmable Architectures (ACM Journal on Emerging Technologies in Computing Systems, 2005) -- most comprehensive single article to date; this is the one article to read to get the current full story [Abstract and ACM Link]
• Seven Strategies for Tolerating Highly Defective Fabrication (IEEE Design and Test of Computers, 2005) -- how will we tolerate fabrication which leaves 1-10% of the wires broken and the junctions disconnected? [Abstract and IEEE Xplore Link]
• Fault-Tolerant Sub-lithographic Design with Rollback Recovery (Nanotechnology, 2008) -- how tolerate transient upsets during operation. [Abstract and IOP Link]
• 3D Nanowire-Based Programmable Logic (Nanonets 2006) -- how to scale designs into three dimensions using multiple layers of nanowires [Abstract and Paper Links]
• Array-Based Architecture for FET-Based, Nanoscale Electronics (IEEE Tr. Nanotechnology, 2003) -- initial outline of how to build fully nanoscale programmable logic arrays using this technology [Abstract, Paper link]
• Nanowire-Based Sublithographic Programmable Logic Arrays (FPGA 2004) -- more concrete details on how to build nanowire PLAs with density calculations. [Abstract, Paper link]
• Design of Programmable Interconnect for Sublithographic Programmable Logic Arrays (FPGA 2005) -- how to interconnect nanowire PLA blocks with mapping and density calculations for larger benchmarks. [Abstract, Paper link]
• Stochastic Assembly of Sublithographic Nanoscale Interfaces (IEEE Tr. Nanotechnology, 2003) -- how to build decoders to bridge between lithographic and sublithographic scale, an important element of bootstrapping to programmability; also outlines nanoscale memory arrays [Abstract, Paper link]
• Radial Addressing of Nanowires (ACM Journal on Emerging Technologies in Computing Systems, 2006) -- a self-aligned technique for building nanoscale decoders to bridge between lithographic and sublithographic scales [abstract and ACM Link]
• Law of Large Numbers System Design (Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation) -- a more overview/tutorial article on coping with and exploiting statistical phenomena at the atomic scale [abstract and citation]
• A Greedy Algorithm for Tolerating Defective Crosspoints in NanoPLA Design (ICFPT 2004) -- a detailed paper with algorithms and analysis for tolerating non-programmable crosspoint defects [abstract and paper links ]
• Non-Photolithographic Nanoscale Memory Density Prospects (IEEE Tr. Nanotechnology, 2005) -- how to organize nanoscale memories and an assessment of the density they can provide with defect accounting [ Abstract, Paper link ]
• Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches (IEEE Tr. Nanotechnology, 2005) -- how to get deterministic addresses and multibit (word-wide) interfaces to stochastically assembled, nanoscale memories [ Abstract, Paper link]
• Fault Tolerant Nano-Memory with Fault Secure Encoder and Decoder (Nanonets, 2007) -- how to build the error-correction circuitry for memories in nanoscale logic and tolerate both defects and transient faults in the ECC logic [ Abstract, Paper link] (basic FSD ideas developed in [DFT 2007 paper]).
• Sub-lithographic Semiconductor Computing Systems (HotChips 2003) -- a short overview of the techniques [Abstract, Paper link]
• Molecular Electronics: Devices, Systems and Tools for Gigagate, Gigabit Chips (ICCAD'02) -- tutorial on emerging technology highlighting EDA challenges [Abstract, Paper link]

Related

• Stochastic Spatial Routing for Reconfigurable Networks (Journal of Microprocessors and Microsystems, 2006) -- complete story on designing devices for self routing; this is a stand-alone description and contains more detailed experiments and evaluation than earlier conference papers (below) [Abstract and DOI Link]
• Hardware-Assisted Simulated Annealing with Application for Fast FPGA Placement (FPGA 2003) -- how to do self placement [Abstract, Paper Link]
• Hardware-Assisted Fast Routing (FCCM 2002) -- first description of how to design devices for self routing [Abstract, Paper Link]
• Stochastic, Spatial Routing for Hypergraphs, Trees, and Meshes (FPGA 2003) -- closing the quality gap and expanding the realm of applicability for self routing [Abstract, Paper Link]