Benjamin Gojman

Email: First letter of first name full last name at seas dot upenn dot edu
Moore 315
3330 Walnut St.
Philadelphia, PA 19104

I am a Ph.D. Candidate in the Computer & Information Science department at the University of Pennsylvania. I am part of the Implementation of Computation Group advised by Professor André DeHon.

Research

Society has been transformed by our ability to do fast, efficient and dependable computation. Nevertheless, this is just the beginning of what will be enable as we continue to push for more reliable, smaller, faster and more energy-efficient circuits. The goal of my research is to propel these improvements. Rather than depend on Moore's Law to achieve this, I discover and analyse alternate dimensions that lead to computational growth.

Currently I take advantage of an "Information Dimension" to understand, mitigate and take advantage of the effects of variation in current and future circuits. This includes variation due to the manufacturing process, as well as variation experienced by the circuit during operation, over its full lifetime.

Specifically I focus on measuring the process variation on commercial off-the-shelf FPGAs at a very fine-grained level. These measurements are then used to improve the energy efficiency of FPGAs.

Recent Publications Full List

  • GROK-INT: Generating Real On-chip Knowledge for Interconnect Delays Using Timing Extraction
    Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '14), May 11-13, 2014

    With continued scaling, all transistors are no longer created equal. The delay of a length 4 horizontal routing segment at coordinates (23,17) will differ from one at (12,14) in the same FPGA and from the same segment in another FPGA. The vendor tools give conservative values for these delays, but knowing exactly what these delays are can be invaluable. In this paper, we show how to obtain this information, inexpensively, using only components that already exist on the FPGA (configurable PLLs, registers, logic, and interconnect). The techniques we present are general and can be used to measure the delays of any resource on any FPGA with these components. We provide general algorithms for identifying the set of useful delay components, the set of measurements necessary to compute these delay components, and the calculations necessary to perform the computation. We demonstrate our techniques on the interconnect for an Altera Cyclone-III (65nm). As a result, we are able to quantify over a 100ps spread in delays for nominally identical routing segments on a single FPGA.

  • GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays using Timing Extraction
    Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth and André DeHon
    To appear in ACM Transactions on Reconfigurable Technology and Systems (TRETS)
    [abstract] [author's copy] [DOI]

    Timing Extraction identifies the delay of fine-grained components within an FPGA. From these computed delays, the delay of any path can be calculated. Moreover, a comparison of the fine-grained delays allows a detailed understanding of the amount and type of process variation that exists in the FPGA. To obtain these delays, Timing Extraction measures, using only resources already available in the FPGA, the delay of a small subset of the total paths in the FPGA. We apply Timing Extraction to the Logic Array Block (LAB) on an Altera Cyclone III FPGA to obtain a view of the delay down to near individual LUT SRAM cell granularity, characterizing components with delays on the order of tens to a few hundred picoseconds with a resolution of ±3.2 ps, matching the expected error bounds. This information reveals that the 65 nm process used has, on average, random variation of σ/μ = 4.0% with components having an average maximum spread of 83 ps. Timing Extraction also shows that as VDD decreases from 1.2 V to 0.9 V in a Cyclone IV 60 nm FPGA, paths slow down and variation increases from σ/μ = 4.3% to σ/μ = 5.8%, a clear indication that lowering VDD magnifies the impact of random variation.

  • GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays using Timing Extraction GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays using Timing Extraction
    Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth and André DeHon
    Proceedings of the 21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '13), February 11-13, 2013

    Timing Extraction identifies the delay of fine-grained components within an FPGA. From these computed delays, the delay of any path can be calculated. Moreover, a comparison of the fine-grained delays allows a detailed understanding of the amount and type of process variation that exists in the FPGA. To obtain these delays, Timing Extraction measures, using only resources already available in the FPGA, the delay of a small subset of the total paths in the FPGA. We apply Timing Extraction to the Logic Array Block (LAB) on an Altera Cyclone III FPGA to obtain a view of the delay down to near individual LUT granularity, characterizing components with delays on the order of a few hundred picoseconds with a resolution of ±3.2 ps. This information reveals that the 65nm process used has, on average, random variation of σ/μ=4.0% with components having an average maximum spread of 83ps. Timing Extraction also shows that as VDD decreases from 1.2V to 0.9V in a Cyclone IV 60nm FPGA, paths slow down and variation increases from σ/μ=4.3% to σ/μ=5.8%, a clear indication that lowering VDD magnifies the impact of random variation.

  • Crystals and Snowflakes: Building Computation from Nanowire Crossbars Crystals and Snowflakes: Building Computation from Nanowire Crossbars
    IEEE Computer, Volume 44, Issue 2, February, 2011

    Suitable architectures and paradigm shifts in assembly and usage models will make it possible to exploit the compactness and energy benefits of single-nanometer dimension devices and allow extending these structures into the third dimension without depending on top-down lithography to define the smallest feature sizes in a system.

Teaching

I've been fortunate to have the opportunity to develop and TA several courses both as a graduate and undergraduate student. For the past several years, however, I've been primarily involved with Digital Audio Basics, helping develop and teach the class, and either TAing or supporting the TA staff.