CSE 371/2:

Digital System Organization and Design

CSE372

Manual

1. HTML format
   • Introduction
   • Lab 1 - Answers
   • Lab 2 - Answers
   • Lab 3 - Answers
   • Lab 4 - Answers
   • Lab 5 - Answers
     Please note: D.E. 2 has been corrected, please see newsgroup for details
   • Lab 6 - Answers
   • Appendix A
   • Appendix B
2. PDF format
   • Introduction
   • Lab 1 - Answers
   • Lab 2 - Answers
   • Lab 3 - Answers
   • Lab 4 - Answers
   • Lab 5 - Answers
     Please note: D.E. 2 has been corrected, please see newsgroup for details
   • Lab 6 - Answers
   • Lab 7
   • Appendix A
   • Appendix B

Statistics

For you number freaks, I have posted a summary of grade statistics:

Download

1. Lab 3, Design Exercise 2 - Diglog three bit parity circuit with INST0 gate attached. Please examine this circuit closely to see how it is configured. Hit shift and click the left mouse button at the same time (assuming you are using Netscape) as this will save the file to disk for you.
2. Linux stuff
   1. Diglog for linux(~700kB) Warning: This is completely unsupported and is provided as a service to those who do not fear screwing up their machines. I will not accept any responsibility for subsequent damage you may cause by trying to install it.
   2. Basic Instructions to install it are provided.
      
   3. New Diglog Gate Library For those that run Diglog under Linux, there was an error in the 74125. This library is fixed. See the newsgroup if you have no idea what I'm talking about.
3. Lab 5, Design Exercise 1 - Diglog circuit for this problem. If you are having problems understanding the exercise, download this circuit and play with it.

upenn.cis.cse371

Related links

comp.arch newsgroup.

comp.arch.arithmetic newsgroup.

Online Chip Directory