We have been introduced to some basic logic devices used in the construction of more complex logic circuits. In this laboratory, we shall discuss some leftover material from section B.3 in P&H, in particular the more complex combinational logic devices.
P&H, Appendix B, Section 3.
for a slight
clarification.)
Figure: The inputs and outputs to the state machine in Exercise B.15
Section B.3 introduces the multiplexor (also known as ``mux'') as a
more advanced, yet still basic, logic device. Figure B.3 depicts a
simple 2-input, 1-bit multiplexor. There is, in general, an
additional ``enable'' input which allows the mux to function normally.
We shall see the usefulness of such an input shortly (we can assume
the devices below have enables as well). Be sure to understand that
not only can there be n data inputs to a mux with
selector inputs, but each data input can be
made of multiple bits, say of size b. The operation of the mux is
then to simply select which set of b bits shows up on the output
pins. Figure is basically a modified Figure B.3.
Also introduced in this section is the decoder. As the name implies, this device converts an encoded input to a different output code. For example, Figure B.4 depicts a 3-to-8 binary decoder that converts a 3-bit binary number into a one-hot or a 1-out-of-m code. This is not the only type of decoder that is available. Another example is a 7-segment decoder, which is/was used widely in circuits designed to drive 7-segment LED/LCD displays. A binary decoder can be used as a ``minterm generator'' to implement a logic function by combining the outputs using logic gates (,e.g. OR gates). Look at Figure B.4 to confirm this fact.
While P&H only mentions the encoder in a sentence, it is also a widely used chip. What is the difference between it and the decoder, when the basic function of a decoder is that it ``converts an encoded input to a different output code?'' While a decoder generally has fewer inputs than outputs, an encoder has more inputs than outputs. In the Design Exercises, we will be looking at one type of encoder, the priority encoder.
One device not mentioned in P&H is the demultiplexor, or demux for short. It is indeed the inverse of a mux: a mux selects from one of n data sources and outputs the selected data, a demux selects one of m outputs and routes the data input there.
The general name for any logic device whose function is programmed by a user after manufacture is called a Programmable Logic Device (PLD). PLAs and ROMs, introduced in the text, are two incarnations of PLDs.
The implementation of a PLA is not as complex as it looks. As the book states, the PLA corresponds to a common-structured implementation of a sum-of-products representation. Pay close attention to the reading; it does explain the basic intuition behind a PLA's usefulness. One question remains, how are PLAs used in ``real life?'' Many times we wish to have the flexibility to change a logic design without having to ``rewire'' a circuit. Say we design a circuit using logic chips (like those mentioned in the previous lab's exercises) with fixed logic functions. If we wished to change the functionality of this circuit, we will most certainly have to change the wiring of the circuit, as well as the chips. What a pain. However, with a PLA, a simple re-programming will make the changes. The same goes for other PLDs. We will see the usefulness of at least the ROM devices in later labs.
outputs of an n-bit binary decoder are generally
used to control a set of devices, where at most one device is
supposed to be active at any one time. Now imagine the converse:
consider a system with inputs, each of which indicates a request
for service. This structure is often found in computer I/O
subsystems, where inputs might be interrupt requests. A binary
encoder might suffice, if only we can guarantee that only one request
comes in at a time. The solution is to assign a priority
to each input, so that the encoder only considers the ``highest
level'' priority request.
We are interested in designing a priority encoder with four inputs
I3-I0. It has two outputs A1-A0 which
indicate the number of the highest priority asserted input, if any.
Another output IDLE indicates an idle condition, where no
inputs are asserted. Figure below depicts the
theoretical logic symbol for this device:
Figure: 4-input priority encoder
