Sequential Logic Basics

 

Purpose

We will now take the next step, and show how combinational logic with feedback can be used to create circuits with memory.

Required Reading

P&H, Appendix B, Sections 4 & 5.

Preparatory Exercises

1. Implement the design of a D latch depicted in Figure B.13 in P&H into Diglog. Verify its operation.
2. Implement the design of a D flip-flop depicted in Figure B.15 in P&H into Diglog. Use the D latch you designed in the previous exercise as an instance gate. Verify its operation.

Discussion

Without going into too much detail, P&H covers most of the basics behind sequential logic. Understanding sequential logic design is essential to the design of a processor (hint). We shall look at two ways to represent the functionality of simple sequential circuits and then look a small case study to demonstrate some of the nuances (pronounced ``pitfalls'') of sequential logic.

Characteristic equations

The functional behavior of a latch or flip-flop can be described by a characteristic equation that simply specifies the ``next state'' of the device as a function of its current state. Figure B.12 in P&H depicts an S-R latch (short for ``Set-Reset'') and we are already familiar with the D latch and D flip-flop. The characteristic equations for these gates are given in Table .

  
Table: Characteristic equations.

Notice the ``*'' suffix. This notation is a standard convention and should be used to indicate ``the next value of Q.'' Note that the equation does not describe the triggering condiction (whether the device is a latch or a flip-flop) but only the logical response to the inputs.

Function Tables

This is another representation of sequential logic circuits. Table  shows the function table for an D flip-flop.

  
Table: Function table for positive-edge triggered D flip-flop.

Notice that when the clock edge rises (positive edge), the output Q does indeed match the input D. When the clock is high or low, nothing changes.

A note on three-state gates

What is this third state? Is it somewhere between high or low (see the Case Study)? No. In effect, when a gate's output is in this third state, it is virtually disconnected from the circuit. We know that we cannot just tie two outputs together if both are outputing a value -- this is electrically incorrect. Play with 74125 gate in Diglog. Turn on glow mode to see when the gate is in its high-impedance state (green color).

What exactly does high-impedance mean? Simply, it means that the output becomes a big resistor, so it appears to be ``floating'' and functionally behaves as if it were not even there.

A Case Study: the S-R latch

Despite the simple characteristic behavior this device has, it does possess an interesting feature. It is by nature a metastable device (discussed in Appendix B, Section 7 in P&H), which means that there is a third equilibrium point, neither high nor low, that the device may wish to be in.

Try the following: make an S-R latch using two NOR gates in Diglog. Connect the S and the R inputs and then attach one switch to the input. Turn glow mode on. Now press the switch on, then off. What do you see? The feedback wires should be flashing wildly. Diglog cannot determine what the correct values should be. Indeed, this is the case because in an analog analysis of the circuit (not necessary to know this) the circuit has a third stable point that occurs when both inputs are set to one, then negated simultaneously. Try using the circuit without the two inputs connected and see that it does operate normally.

As John Wakerly puts it, ``If the simplest sequential circuit is susceptible to metastable behavior, you can be sure that all sequential circuits are susceptible. And this behavior is not only something that occurs at power up.''

Design Exercises

1. One standard flip-flop is called the JK flip-flop (called JKPOS or JKNEG in Diglog). Table  is the function table for a positive-edge triggered JK flip-flop.
   1. Design a negative edge triggered JK flip-flop using a positive-edge triggered D flip-flop (DPOS) and some extra combinational gates (should be just a few simple ones).
   2. What is its characteristic equation (for Q)? Also, in a couple of sentences, explain why this equation makes sense.

     
   Table: Function table for positive-edge triggered JK flip-flop.
   

2. Another standard flip-flop is called a T flip-flop (called TPOS or TNEG in Diglog). It changes its output every tick of the clock signal. This means that the Q output signal has half the frequency of the input T signal.
   1. Design a positive edge triggered T flip-flop with enable using a D flip-flop and some logic. The enable just affects whether the flip-flop is ``ignoring'' the input signal T or not.
   2. Design a positive edge triggered T flip-flop with enable using only a JK flip-flop.
   3. What is its characteristic equation (with enable)?
3. Implement the SRAM depicted in Figure B.23 in P&H. Notice how the outputs of some latches are tied together, which you could not normally do unless the outputs were tri-state capable. So use an instance to make a D latch with an enable (choose active high or low). Also, use a 74125 three-state buffer. Use a 74139 2-to-4 decoder, but watch out -- it has active low outputs, so you might have to modify the logic a bit.