Announcements and Addenda

A few things that have come up:

• When the write_interval signal is high, the timer should internally latch the interval_in value. The timer is memory mapped and so interval_in is effectively the store data value. You cannot count on this bus having the desired value whenever the timer needs to be reset.
• The usage model of the timer is write the interval once (or a few times) but then read the status many times, i.e., in a loop waiting for the timer to go off. And so the important semantics of the interface have to do with read_status. As for the semantics of write_interval, you should resolve any ambiguity in the direction that is simpler in your design. In other words, if resetting the timer any time write_interface is high is simpler, do that. Otherwise, don't.

Instructions

Before you begin, you'll want to walk through the tutorial.

In this lab, you'll be writing code for a simple timer device. The timer is one of the memory mapped devices available via the LC4 ISA and the only one you can reasonably write yourself.

Four files have been supplied for you:

• register.v: contains verilog code for an N-bit register.
• lab0.v: contains wrapper code that instantiates the timer.
• lab0.ucf: assigns wrapper interface signals to FPGA pins.
• timer.v: contains skeleton module code for the timer.

When you create your project, you can simply copy these files into the project directory and then add them. Your job is to write the module code for timer.v.

The timer device has the following interface:

• single bit inputs CLK, GWE, and RST. These are the global clock, write-enable, and reset signals that you should connect to any registers used inside the timer.
• 16-bit interval_in input. This is the value of the timer interval in ms (milli-seconds).
• 1-bit write_interval input. When this signal is 1 the timer interval register is written with the current interval_in value.
• 1-bit status_out output. The value of this output is 1 if the timer has "gone off" and the timer has not been read yet. Otherwise it is 0.
• 1-bit read_status input. When this signal is 1 and the timer has "gone off", the timer is reset.

You should implement this interface using the given Nbit_reg register primitives and combinational logic.

The timer device is instantiated by a harness module which connects the timer to buttons and LED's on the daughter board (the little board that connects to the side of the main board). In addition to instantiating the timer, the harness module connects BTN5 to LED8 on the daughter board so that the LED will light up when the button is pressed. You can use this function to test the board and your setup before you have even coded up your timer.

As for the timer, the write_interval and read_status signals are connected to BTN1 and BTN2, respectively. The status_out signal is connected to LED1. The interval_in bus is connected to a hardwired value of 3000 ms (i.e., 3 seconds). The desired behavior of the timer is as follows. You push BTN1 to write the 3 second interval to the timer. 3 seconds later, the timer should "go off" and LED1 should light. Pressing BTN2 should reset the timer (and turn off LED1) if the timer has gone off. Otherwise, it should do nothing. In other words, LED1 should light 3 seconds after the timer was reset regardless of how many times BTN2 was pressed in the meantime.

The clock the harness is connected to is the 32MHz system "ACE" clock. You will need to figure out to convert a number specified in ms (e.g., 3000) to clock ticks.

Demo

When you've completed and tested your design, demo your design to one of the TAs. They will verify the design works correctly and ask you a few questions about the design. If you pass the demo, they will check you off.

What to Turn In

Turn in the follow items in class:

• A printout of your implementation of timer.v
• Answers to the following two questions:
  1. How long did each of you spend on this lab?
  2. What problems (if any) did you encounter while doing this lab?