# VERSION 1.1

NET "CLK_32MHz"  LOC = "AH15"  ;

NET "CLK_32MHz" TNM_NET = "FPGA_SYSTEMACE_CLOCK";
TIMESPEC "TS_FPGA_SYSTEMACE_CLOCK" = PERIOD "FPGA_SYSTEMACE_CLOCK" 31.25 ns HIGH 50 %;

NET "LDGND"  LOC = "V7"  ;
NET "WRITE_INTERVAL_BTN_IN"  LOC = "P3"  ; 
NET "READ_STATUS_BTN_IN"  LOC = "P2"  ; 
NET "TEST_BTN_IN"  LOC = "AA1"  ;
NET "TEST_LED_OUT"  LOC = "V6"  ;  
NET "STATUS_LED_OUT"  LOC = "T8"  ;