`ifndef LOGIC_REGISTER_V
`define LOGIC_REGISTER_V

`timescale 1ns / 1ps

// VERSION 1.1

/* A parameterized-width positive-edge-trigged register, with synchronous reset. 
   The value to take on after a reset is the 2nd parameter. */
module Nbit_reg(in, out, clk, we, gwe, rst);
   parameter n = 1;
   parameter r = 0;
   
   output [n-1:0] out;
   input [n-1:0]  in;   
   input          clk;
   input          we;
   input          gwe;
   input          rst;      

   wire real_we;
   and (real_we, we, gwe);

   reg [n-1:0] state;

   assign #(1) out = state;

   always @(posedge clk) 
     begin 
       if (rst) 
         state = r;
       else if (real_we) 
         state = in; 
     end
endmodule

module Nbit_reg_gsrst( in, out, clk, we, gwe, rst);
   parameter n = 1;
   parameter r = 0;
   
   output [n-1:0] out;
   input [n-1:0]  in;   
   input          clk;
   input          we;
   input          gwe;
   input          rst;      

   wire real_we;
   and (real_we, we, gwe);

	wire real_rst;
	and (real_rst, rst, gwe);
	
   reg [n-1:0] state;

   assign #(1) out = state;

   always @(posedge clk) 
     begin 
       if (real_rst) 
         state = r;
       else if (real_we) 
         state = in; 
     end
endmodule
`endif