`timescale 1ns / 1ps

`define EOF 32'hFFFF_FFFF
`define NEWLINE 10
`define NULL 0

// Kind of bogus because this testbench won't run under ICARUS anyway for lack of file IO
`ifdef ICARUS
 `include "lc4_regfile.v"
`endif

module testbench_v;

	// Inputs
	reg wen;
	reg rst;
	reg clk;
	reg gwe;

    	reg[2:0] rsel1;
	reg[2:0] rsel2;
	reg[2:0] wsel;
	
	reg[15:0] wdata;

	// Outputs
	wire[15:0] rdata1;
	wire[15:0] rdata2;

	// Instantiate the Unit Under Test (UUT)
   
	lc4_regfile myRegfile (.r1sel(rsel1),
			       .r2sel(rsel2),
			       .wsel(wsel),
			       .r1data(rdata1),	
			       .r2data(rdata2),	
			       .wdata(wdata),
			       .we(wen),
			       .gwe(gwe),
		.rst(rst),
		.clk(clk)
	);
   
   	integer file, char, retval, errors;
   	reg[15:0] expectedValue1;
	reg[15:0] expectedValue2;
	
	always #5 clk <= ~clk;

	initial begin

	// Initialize Inputs
	rsel1 = 0;
	rsel2 = 0;
	wsel = 0;
	wen = 0;
	rst = 1;
	wdata = 0;
	clk = 0;
	gwe = 1;	
        errors = 0;

	// open the test inputs
	file = $fopen("regfile.input.test", "r");
	if (file == `NULL)      
        	$finish;

	// Wait 100 ns for global reset to finish
	#100;
	       
	#5 rst = 0;

	char = $fgetc(file);
	while (char != `EOF)
        begin
                  
        if (char == "#")  // eat a comment line
            begin
            while (char != `NEWLINE)
               begin
               char = $fgetc(file);
               end
            end
        else
          
            begin
            
            retval = $ungetc(char, file); // push back the non-comment char
            
            #1
            retval = $fscanf(file, "%b %b %b %b %d %d %d", rsel1, rsel2, wsel, wen, wdata, expectedValue1, expectedValue2);          
            #8 //once every clock cycle

            if (rdata1 != expectedValue1)
               begin
               $display("Error: Value of register %b on output 1 should have been %d, but was %d instead",rsel1, expectedValue1,rdata1 );
               errors = errors + 1;
               end
            if (rdata2 != expectedValue2)
               begin
               $display("Error: Value of register %b on output 2 should have been %d, but was %d instead",rsel2, expectedValue2,rdata2 );
               errors = errors + 1; 
               end
	
            #1
            char = $fgetc(file);
            
            end
         end // end while

        $fclose(file);
        $display("Simulation finished with %d errors", errors);
        $finish;
	end
      
endmodule