`timescale 1ns / 1ps

`ifdef ICARUS
 `include "include/bram.v"
 `include "include/clock_util.v"
 `include "lc4_single.v"
`endif 
  
// VERSION 1.3

module test_lc4_single_v;

   // Global signals	
   reg CLK, RST;
	wire GWE;
	
   // Procesor-memory interconnect
   wire DMEM_WE;
   wire [15:0] IMEM_ADDR, IMEM_OUT, DMEM_ADDR, DMEM_OUT, DMEM_IN;

   // Instantiate processor and memory, but not devices 
   bram memory (.idclk(CLK ), 
   		.iaddr(IMEM_ADDR), .iout(IMEM_OUT), 
		   .daddr(DMEM_ADDR), .dout(DMEM_OUT), 
		   .din(DMEM_IN), .dwe(DMEM_WE),
			.vaddr(), .vout(), .vclk());

   lc4_single lc4 (.CLK(CLK), .RST(RST), .GWE(GWE), 
		   .IMEM_ADDR(IMEM_ADDR), .IMEM_OUT(IMEM_OUT),  
		   .DMEM_ADDR(DMEM_ADDR), .DMEM_IN(DMEM_IN), 
		   .DMEM_OUT(DMEM_OUT), .DMEM_WE(DMEM_WE));
   
   // generate clock and global write enable signal
   always #5 CLK <= ~CLK;
	
   count #(2) GWE_count(.clk( CLK ), .out( GWE ));
   
	// Initialize system
   initial begin
      CLK = 0;
      RST = 0;
      // Reset 
      #20; RST = 1;
      #125; RST = 0;
   end 
   // At every "big clock" edge
   always @(posedge GWE)
     begin
	// Display instruction PC and bits
	$display("PC: %h INSN: %h", IMEM_ADDR, IMEM_OUT);
	// Break, wait for continue
	$stop;
     end
   
endmodule