"Screwdriver" Cache Coherence for Multicore Processors

Peter Hornyack

Faculty Advisor: Dr. Milo M. K. Martin


As the performance limitations of single-core processors are reached, multiprocessing, or linking together multiple processor cores to compute in parallel, is becoming the favored method of increasing computer performance. One of the main difficulties with multiprocessing is cache coherence, or making sure that different processors accessing the same memory do not interfere with each other. ÒScrewdriverÓ is a cache coherence protocol inspired by recently proposed protocols that attempt to advance past the limitations of traditional shared-bus and directory based coherence protocols. Screwdriver incorporates many of the features of these advanced protocols to create a design that avoids race conditions and is easily scalable. Screwdriver was implemented using the Verilog hardware description language (HDL) to allow for realistic simulation as well as physical instantiation on an FPGA. The use of HDL code also allowed the protocol to be evaluated for multiprocessor systems of up to 16 processor cores. The Screwdriver protocol implementation was found to be scalable to some degree, but was limited by the bandwidth of its single memory controller as the number of processors in the system increased.