Welcome to

the Moore School of Electrical Engineering

EE 560 (Digital IC and VLSI Fundamentals)

User's Guide to Cadence version 4.4.5



Setting Up Your Unix Environment

Starting Cadence

Create Libraries

Schematic entry using Composer

Create Symbols

Simulation with Verilog-XL

Simulation with Hspice

Custom Layout using Virtuoso

Design Rule Check (DRC)

Layout Versus Schematic (LVS) Verification using Diva

Post Layout Simulation

Connecting I/O Pads to Layout (Not Available)  To be written!!

CIF Conversions (CIF IN; CIF OUT)

Sending your IC Chip to MOSIS for Fabrication

Cadence Online Help Manual

First created by Lin Ping Ang, 1997 for Cadence 4.3
Redesigned and rewritten by Sameer Sonkusale for cadence 4.4.3 (dated Feb1st, 2000)
Last updated on April 4th, 2000 for cadence 4.4.5
All questions and comments can be directed to sameers@ee.upenn.edu