Introduction
Setting Up Your Unix Environment
Starting Cadence
Create Libraries
Schematic entry using Composer
Create Symbols
Simulation with Verilog-XL
Simulation with Hspice
Custom Layout using Virtuoso
Design Rule Check (DRC)
Layout Versus Schematic (LVS) Verification using Diva
Post Layout Simulation
Connecting I/O Pads to Layout (Not Available) To
be written!!
CIF Conversions (CIF IN; CIF OUT)
Sending your IC Chip to MOSIS for Fabrication
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