UNIVERSITY of PENNSYLVANIA
Department of Electrical and Systems
Engineering
ESE170: Principles of Digital Design
Prof: Jan Van der Spiegel
Spring 2012
Syllabus (tentative)
|
No. |
Spring 2012 |
TOPIC |
Reading |
Lab Schedule |
|
|
Date |
Text: Logic and Computer Design Fundamentals, Mano and Kime (4th Edition) |
Textbook section |
|
|
1 |
1/11/2012 |
Introduction to Digital Systems; levels of abstraction; information representation; course objectives. |
1-1 |
No Lab |
|
2 |
1/13/2012 |
Number systems; Conversion between number systems |
1-2, 1-3 |
|
|
|
1/16/2012 |
Martin Luther King Jr. Day - no class |
|
No Lab |
|
3 |
1/18/2012 |
ASCII Code; Decimal and Gray codes |
1-4, 1-5, 1-6 |
Lab 0: Intro and Xilinx Tutorial (Half-Adder) |
|
4 |
1/20/2012 |
Binary logic; Boolean Algebra (basic identities). |
2-1, 2-2 |
|
|
5 |
1/23/2012 |
Standard forms |
2-3, Theorems |
Lab 1: Full Adder |
|
6 |
1/25/2012 |
Circuit Optimization and K-maps |
2-4, 2-5 |
|
|
7 |
1/27/2012 |
Map manipulation (implicants), don't cares |
2-5 |
|
|
8 |
1/30/2012 |
Other gate types, XOR gates; Hi-impedance outputs |
2-8, 2-9, 2-10 |
Lab 2: Traffic Light Controller |
|
9 |
2/1/2012 |
Iterative circuits, Binary Adders |
4-1, 4-2 |
|
|
10 |
2/3/2012 |
Binary subtractor; Signed binary adder-subtractor. |
4-3, 4-4 |
|
|
11 |
2/6/2012 |
Signed binary Addition and Subtraction |
4-4, 4-5 |
Lab 3: Four-bit Adder |
|
12 |
2/8/2012 |
Binary Multiplication;Design Procedure; Hierarchical Design; Tech. mapping |
4-5; 3-1, 3-2, 3-3, 3-4 |
|
|
13 |
2/10/2012 |
Combinational Functional Block: Decoders |
3-7 |
|
|
14 |
2/13/2012 |
Combinational Functional Block: Encoders |
3-7 |
Lab 4: Combination Multiplier (Week 1) |
|
15 |
2/15/2012 |
Multiplexers and Applications |
3-8 |
|
|
16 |
2/17/2012 |
Sequential circuits; latches |
5-1; 5-2 |
|
|
17 |
2/20/2012 |
Review Combinational Circuits |
|
Lab 4: Comb. Mult. (Week 2) |
|
18 |
2/22/2012 |
Midterm 1 (Combinational Logic) |
|
|
|
19 |
2/24/2012 |
Latches (cont), Flip-flops |
5-2, 5-3 |
|
|
20 |
2/27/2012 |
Flip-flops (cont) |
5-3 |
Floating Week |
|
21 |
2/29/2012 |
Sequential circuit analysis |
5-4 |
|
|
22 |
3/2/2012 |
Sequential circuit analysis and review midterm |
5-4 |
|
|
|
3/5-9/12 |
Spring Break |
|
|
|
23 |
3/12/2012 |
Sequential circuit analysis; design |
5-5 |
Lab 5: ALU (Week 1) |
|
24 |
3/14/2012 |
Sequential circuit design (cont) |
5-5 |
|
|
25 |
3/16/2012 |
Sequential circuit design: unused states and verification (timing issues in Mealy machines) |
5-6 |
|
|
26 |
3/19/2012 |
Other flip-flop types |
5-6 |
Lab 5: ALU (Week 2) |
|
27 |
3/21/2012 |
State machine diagrams and constraints |
5-7 |
|
|
28 |
3/23/2012 |
State machine diagrams - examples |
5-7 |
|
|
29 |
3/26/2012 |
Practical Considerations (debouncing, synchronizer, metastability); delay and timing. |
5-7 ; 6-2, 6-3 |
Lab 6: VGA Controller |
|
30 |
3/28/2012 |
Timing in
sequential circuits; Registers, Register Transfers and Micro-operations |
7-6 |
|
|
31 |
3/30/2012 |
Shift
Registers and Counters |
6-4, 7-1,
7-2, 7-3 |
|
|
32 |
4/2/2012 |
Shift Registers and Counters (cont.) |
7-5, 7-6 |
Lab 7: RPN Calculator |
|
33 |
4/4/2012 |
Midterm 2 (Sequential Logic) |
||
|
34 |
4/6/2012 |
Counters (cont.) |
7-6 |
|
|
35 |
4/9/2012 |
Register-cell design and MUX-based transfers |
7-7, 7-8 |
Lab 8: Pong Game (Week 1) |
|
36 |
4/11/2012 |
MUX-based and Bus-based transfers; Control of Register Transfers |
7-8, 7-9, 7-10 |
|
|
37 |
4/13/2012 |
Control of Register Transfers (cont.) |
7-10 |
|
|
38 |
4/16/2012 |
Tri-State Bus based transfers; serial transfers |
7-8, 7-9 |
Lab 8: Pong Game (Week 2) |
|
39 |
4/18/2012 |
Examples of Control of Register Transfers; micro-programmed control |
7-10, 7-13 |
|
|
40 |
4/20/2012 |
Propagation delay, Flip-flop timing |
6-2, 6-3, 6-4 |
|
|
41 |
4/23/2012 |
Programmable Logic Implementations |
6-8 6-4 |
|
|
|
Tuesday |
Final Examination (see Registrar Website for full schedule) |
Cumulative |
|
Updated March
27, 2012
Created by Jan Van der Spiegel