UNIVERSITY of PENNSYLVANIA
Department of Electrical and Systems Engineering

ESE171: Principles of Digital Design Laboratory

Spring 2012

Syllabus

Lab Day

Lab Topic

Reports
January 17
January 20
January 23		 Lab 0: Intro to ESE171, Group formation, Intro to Xilinx (Part 1)
January 23
January 24
January 27

Lab 1: Introduction to the Xilinx Toolchain (Part 2)

  • Safety issues
  • Full Adder
  • Using skills learned in half adder tutorial to build a full adder
January 30
January 31
February 3

Lab 2: Traffic Light Controller

  • Convert truth tables to combinational circuits
  • Design of a decoder for a 7-segment display
  • Use of buses
  • Use of the pattern wizard for test bench waveforms
  • VHDL (hardware description language)
 Lab 2: Discussion Questions
(Due Fri. 2/10)
February 6
February 7
February 10

Lab 3: Four-bit Adder

  • Design and simulation of a 4-bit adder
  • VHDL (Hardware description language)
  • 7-segment decoder
February 13
February 14
February 17

Lab 4: Combinational Multiplier

  • 4-bit by 4-bit multiplier
  • Binary-to-BCD conversion
  • Timing Constraints
  • Reading ISE Reports
  • VHDL Testbenches
February 20
February 21
February 24		 Lab 4: Combinational Multiplier (continued)
Feb. 27-Mar. 2
(by appt. only)		 Lab 4: Combinational Multiplier demo (only if needed) Report 1: Combinational Multiplier
(Due Fri. Mar 2 at 11:59pm)
March 5-9 Spring Break
March 12
March 13
March 16

Lab 5: ALU Design and Implementation

  • Design a 8-bit ALU
  • Use of the Core Generator
  • Implementation and testing the ALU
  • VHDL Testbenches
March 19
March 20
March 23		 Lab 5: ALU (continued)
March 26
March 27
March 30

Lab 6: FSMs and VGA Controller

  • Implementing finite state machines
  • Using the IP Core Generator
  • Using VHDL Processes
April 2
April 3
April 6

Lab 7: RPN Calculator

  • Shift registers
 Lab 6 Discussion Questions
April 9
April 10
April 13

Lab 8 (Final Project): The Game of Pong

  • State Machine Diagrams
  • Registers and memory
  • Decoding
April 16
April 17
April 20		 Lab 8 (Final Project): The Game of Pong (continued) Report 3: ALU and Calculator

Supported by a grant of Xilinx Corporation

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Last updated January 16, 2012
Created by Jan Van der Spiegel