UNIVERSITY of PENNSYLVANIA
Department of Electrical and Systems Engineering

ESE171: Principles of Digital Design Laboratory

 

Spring 2015

 


 

Syllabus

 

Lab Day

Lab Topic

Reports


January 21
January 23

Lab 0: Intro to ESE171, Group formation, Intro to Xilinx (Part 1)

January 26
January 27
January 30

Lab 1: Introduction to the Xilinx Toolchain (Part 2)

 

  • Safety issues
  • Full Adder
  • Using skills learned in half adder tutorial to build a full adder
February 2
February 3
February 6

Lab 2: Traffic Light Controller

 

  • Convert truth tables to combinational circuits
  • Design of a decoder for a 7-segment display
  • Use of buses
  • Use of the pattern wizard for test bench waveforms
  • VHDL (hardware description language)
Lab 2 Discussion Questions: TBA
February 9
February 10
February 13

Lab 3: Four-bit Adder

  • Design and simulation of a 4-bit adder
  • VHDL (Hardware description language)
  • 7-segment decoder
February 16
February 17
February 20

Lab 4: Combinational Multiplier

  • 4-bit by 4-bit multiplier
  • Binary-to-BCD conversion
  • Timing Constraints
  • Reading ISE Reports
  • VHDL Testbenches
February 23
February 24
February 27
Lab 4: Combinational Multiplier (continued)
Mar 2-Mar 6
(by appt. only)
Lab 4: Combinational Multiplier demo (only if needed) Report 1: Combinational Multiplier
(Due Fri. Mar 7 at 11:59pm)
March 7-15 Spring Break
March 16
March 17
March 20

Lab 5: ALU Design and Implementation

 

  • Design a 8-bit ALU
  • Use of the Core Generator
  • Implementation and testing the ALU
  • VHDL Testbenches
March 23
March 24
March 27
Lab 5: ALU (continued)
March 30
March 31
April 3

Lab 6: FSMs and VGA Controller

 

  • Implementing finite state machines
  • Using the IP Core Generator
  • Using VHDL Processes
April 6
April 7
April 10

Lab 7: RPN Calculator

 

  • Shift registers
Lab 6 Discussion Questions
April 13
April 14
April 17

Lab 8 (Final Project): The Game of Pong

  • State Machine Diagrams
  • Registers and memory
  • Decoding
April 20
April 21
April 24
Lab 8 (Final Project): The Game of Pong (continued) Report 2: ALU and Calculator


 

Supported by a grant of Xilinx Corporation

 


 

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Last Updated: December 5, 2014