VHDL Reserved Keywords

Words that cannot be used in other contexts (module/signal names, etc.)


Reserved words in VHDL

abs

access

after

alias

all

and

architecture

array

assert

attribute

begin

block

body

buffer

bus

case

component

configuration

constant

 

 

disconnect

downto

else

elsif

end

entity

exit

file

for

function

generate

generic

group

guarded

if

impure

in

inertial

inout

 

 

is

label

library

linkage

literal

loop

map

mod

nand

new

next

nor

not

null

of

on

open

or

others

 

 

out

package

port

postponed

procedure

process

pure

range

record

register

reject

return

rol

ror

select

severity

signal

shared

sla

sli

sra

srl

subtype

then

to

transport

type

unaffected

units

until

use

variable

wait

when

while

with

xnor

xor

 

 

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