ESE200: Principles of Digital Design
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(URL: http://www.seas.upenn.edu/~ese200) |
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| Fall 2008 |
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Reading | ||
| Date | Text: Logic and Computer Design Fundamentals, Mano and Kime (4th Edition) | Textbook section |
Labs |
HW due date |
| Sep.4 | Digital Systems; Number systems; Arithmetic operation; ASCII Code; Decimal and Gray codes | 1-1, 1-2, 1-3, 1-4, 1-5, 1-6 | No lab first week of Class | |
| Sep.9 | Binary logic; Boolean Algebra (basic identities). | 2-1, 2-2 | Lab 1 [1st lab Tue Sep. 12 and Fr. 15th] | |
| Sep.11 | Boolean Algebra (cont.); Standard forms | 2-2, 2-3, Theorems | HW1 | |
| Sep. 16 | Two-level optimization (K-maps); Map manipulation (implicants, don't cares, product of sumes) | 2-4, 2-5 | Lab 2 | |
| Sep. 18 | Other gate types; XOR gates; Hi-impedance outputs | 2-8, 2-9, 2-10 | HW2 | |
| Sep. 23 | Iterative circuits, Binary Adders; Carry-look-ahead | 4-1, 4-2, handout | Lab 3 | |
| Sep. 25 | Binary subtractor; Signed binary addition - subtraction. | 4-3, 4-4 | HW3 | |
| Sep. 30 | Other arithmetic functions: multiplier; Design Procedure; Hierarchical Design; Tech. mapping; Decoders | 4-5; 3-1, 3-2, 3-3, 3-4, 3-7 | Lab 4 | |
| Oct. 2 | Combinational Functional Block: Decoding, Encoding and Multiplexers | 3-8, 3-9 | HW4 | |
| Oct. 7 | Sequential circuits; latches | 5-1; 5-2 | Lab 4 cont. | |
| Oct. 9 | Flip-flops | 5-3 | HW5 | |
| Oct.14 | Fall Break | No lab this week | ||
| Oct. 16 | Sequential circuit analysis | 5-4 | HW6 | |
| Oct. 21 | Exam 1 - | Lab 5 | ||
| Oct. 23 | Sequential circuit desing | 5-5 | ||
| Oct. 28 | Sequential circuit design | 5-5 | Lab 6 | |
| Oct. 30 |
Other flip-flop types |
5-6 | HW7 | |
| Nov. 4 | State machine diagrams and applications | 5-7 | Lab 7 | |
| Nov. 6 | State machine diagrams and applications (cont); debouncing | 5-7 | HW8 | |
| Nov. 11 | Registers and Shift Registers |
7-1, 7-6 (partly) |
Lab 8 | |
| Nov. 13 |
Register transfer operations; Microoprations; Operations on Single register; counters |
7-2, 7-3, 7-5, 7-6 | HW9 | |
| Nov. 18 | Register-cell design; |
7-7, 7-8 |
Lab 9 | |
| Nov. 20 | Exam 2 - | |||
| Nov. 25 | Multiplexer and bus-based transfers; Serial transfer and microoperations. | 7-8, 7-9 | No lab | HW10 |
| Nov. 27 | Thanksgiving |
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| Dec. 2 | Control of Register Transfers | 7-10 | Lab 9 (cont.) | |
| Dec. 4 | Control of Register Transfers | 7-10 | HW11 | |
| Dec. 10, 9-11am | Final Examination (check registrar for confirmation) - LRSM Auditorium | |||