ESE 201: Principles of Digital Design Laboratory
Fall 2008
Do not print copies of this material on the CETS or ESE printers.
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 Tutorials ______ |
Prototyping board: Digilab XL board |
Device pins ______________ |
XST Software manual |
The laboratory consists of hands-on assignments which accompany the lectures of ESE200. The goal is to illustrate concepts discussed in the class and to give the students the opportunity to build and test real systems.
The lab exercises will make use of the Xilinx Foundation(TM) System which is a a powerful state-of-the-art CAD tool for designing and implementating digital systems on Field Programmable devices (FGPAs or CPLDs). The ESE Undergraduate lab (Frederick Ketterer Lab) is equipped with both the Xilinx Foundation software tools and the Digilab boards to download and test the designs. The system consists of an integrated set of tools that allows one to capture designs (with schematic entry or a Hardware Description Language), simulate, implement and test them. The use of programmable logic devices takes away the tedious task of wire wrapping individual gates and allows one to concentrate on the creative part of designing the circuits.
The assignments will introduce you gradually to the Xilinx tools and will serve to illustrate the material covered in class. The first labs deal with combinational circuits and the last ones covers sequential circuits. When you read the lab assignments you will notice that there are several options for the implementation, depending which hardware board you will be using. Unless otherwise specified, you will be using the Digilab board.
Labs are done in groups of two, except for the on-line pre-lab that has to
be done by each student (see also Lab
Procedures).
Course Outcomes
The goals of this laboratory course is:
- To apply concepts and methods of digital system design techniques as discussed in the class (ESE200) through hands-on projects. [a]
- Learn to design combinational and sequential digital systems starting from a word description that performs a set of specified tasks and functions.[c]
- To analyze the results of logic and timing simulations and to use these simulation results to debug digital systems.[b]
- Develop skills, techniques and learn state-of-the-art engineering tools (such as VHDL, Xilinx tools) to design, implement and test modern-day digital systems on FPGAs [i]
- Learning through hands-on experimentation the Xilinx tools for FPGA design as well as the basics of VHDL to design and simulate digital systems. [k]
Place
Frederick Ketterer Lab, room 204 MooreSchedule
Tuesdays 3-6pm
Friday 3-6pm
Friday 12-3pm
Prof. J. Van der Spiegel: (room 203 Moore)
Thursday: 4:00-5:30pm
Policies
Dan Lustig
Andrew Avrin
Rohit Chandra
The on-line pre-lab questions need to be answered prior to coming to the lab. The deadline is indicated in the lab-write up. NO CREDIT will be given for submissions past the deadline! For grading policies consult the individual pre-labs. For late lab policies, please consult the Website in Blackboard.
The final grade will be based on your pre-lab performance, in-lab performance, Lab reports (see Lab Reports), Lab Notebooks and a final in-lab exam. Most of the labs have also an "Honor" section that allows you to receive Honor Points. The honors points in the lab will be graded and recorded separately from the regular lab assignment. They will be used as a reference in determining your final grade.
If you have questions about the grading of the lab report, you have to contact the instructor within one week after the lab reports have been returned. After this week, no changes of grade will be made.
Using or attempting to use unauthorized assistance,
material, or lab results or solutions (in part or whole) is
a violation of the Code of
Academic Integrity and will result in a zero grade for the course.
Supported by a grant of Xilinx Corporation
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Updated July 28, 2008.
