Circuit-Level Modeling, Design, and Optimization for
Units: 1.0 CU
Next Offered: Fall 2014
When: MWF 12-1pm
Where: Towne 307
Instructor: DeHon (office Hour: T4:15pm-5:30pm)
TA: Hyunseok Park (seas: parkhyu)
(office hours: MW7pm-8pm K-Lab)
Catalog Level Description:
Circuit-level design and modeling of
gates, storage, and interconnect. Emphasis on understanding physical
aspects which drive energy, delay, area, and noise in digital
circuits. Impact of physical effects on design and achievable performance.
Role and Objectives
The goal of this course is to teach students what they need to know about
the physical aspects (area, delay, energy, noise) of electronic circuits to
support high-speed, low-energy, area-efficient design of robust digital and
Students will learn:
This course comes after a basic introduction to devices and circuits
(ESE215) and a course on gate-level digital design (ESE170/171). It
should serve both students who will go on to do circuit-level design and
those who will work primarily at higher levels and need to be able to
reason about technology and fundamental limits to establish capabilities
and understand the circuit-level impact of optimizations they perform
at higher levels of design. This will be the most detailed class on
physical issues required for CMPE BSE students. Students may choose to
continue with more advanced circuit and VLSI courses (e.g., ESE570).
- disciplines for robust digital logic and signaling
(e.g., restoration, clocking, handshaking)
- where delay, energy, area, and noise arises in gates, memory, and
- how to model these physical effects both for back-of-the-envelope
design (e.g. RC and Elmore delay) and detailed simulation (e.g., SPICE)
- the nature of tradeoffs in optimization
- how to design and optimize logic, memory, and interconnect structures
at the gate, transistor, and wire level
- how technology scales and its impact on digital circuits and computer
Rough Syllabus (by weeks)
- Review transistor, introduce MOS model
- Gates and restoration, basic gate delay, review transient response
- MOS Transistors (models with physical device parameters
(W,L,Na...)), scaling, variation
- Energy, Delay, Area implications and tradeoffs for MOS circuits
- Clocking, latches, flip-flops (setup, hold, clock skew)
- Other gate models (ratioed, pre/post-charge)
- RC Wire delay and Elmore delay (fanout, transistor sizing)
- Wire Effects (buffering, capacitive coupling/crosstalk)
- RAM design
- Noise: inductive coupling, ground bounce, ionizing particles,
- Transmission lines
- High speed chip-to-chip signaling
- Energy and entropy
2014 course calendar for day-by-day calendar with assignments.
- Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. Digital Integrated Circuits, A Design Perspective, 2nd edition, Prentice
- Errata for text
Grading is based on weekly assignments and a longer end-of-term assignment.
Projects: Two two-week design/optimization projects: (1)
transistor design and optimization for logic/gates and (2) memory design.
- Weekly Assignments [25%]
- Projects [30%]
- Midterms [20%]
- Final [25%]
Writeups must be done in electronic form and submitted through Canvas (next paragraph).
Use CAD or drawing tools where appropriate. Use electric where
required (for drawing up circuit diagrams). Use LaTex, Microsoft Word, or Google Docs for writeups (each provides an equation
editor function, which you will need to use for writing up your equations).
Handwritten assignments and hand-drawn figures are not acceptable. Equations which are typed up but not formatted
(such as through the Word equation editor or LaTex) are not acceptable. Unacceptable submissions
will be automatically marked half off for each unacceptable entry. Illegible submissions will not be graded.
All assignments will be turned in electronically through the Penn Canvas
website. Log in to canvas with your PennKey and password, then select ESE 370 from the Courses and Groups dropdown menu.
Select Assignments from the links on the left and select the assignment you wish to submit for. Submissions should be as an
archive (either .zip or .tar) and conform to the standards below.
The submitted archive must contain the following and be named
- Your writeup as a PDF document.
- All spice decks you generated.
- Your final electric archive (Use the cross-library copy functionality of electric to submit only the relevant .sch files.
For your submission, create a new library and name it
<YourPennKey>_<HomeworkNumber>, then use Cell -> Cross Library Copy
to copy the appropriate .sch files to the new library. Save the library and submit.
- Any additional files required in the assignment
Assignments must be turned in by the published due date to receive full
As a new experiment this term, we will create two separate assignment
turnins---one for late assignments. If you have only finished part of the
assignment before the deadline, turn it in to the on-time. When you finish
the rest, turn it in to the late assignment slot. You will get full credit
for the part turned in on time and partial credit on the part turned in
late. This is intended to remove any dissincentives to turn in the work
you've done before the deadline on time.
We deduct 20% of the homework component grade for each day late.
If assignments or exams fall due on a religious holiday, please make arrangements
with the instructor to accommodate before the posted due date.
Use the Penn Course Absence Report (CAR) in Penn-in-Touch to report
Make sure you call any problems with grading to your TA's attention
immediately and not later than the next class meeting after they are
posted on blackboard. Our TA will be responsible for adjudicating these
problems---the instructors will only be involved as a possible court of last
appeal in case there is some truly difficult decision to make (i.e., in
most cases, we will not be willing to second guess the TA's decisions). To
submit a request to the TA for a review of a credit assignment on a lab
assignment send an email to the TA stating the nature of the problem and
the remedy you desire. We have instructed the TAs not to
consider any requests for grade adjustments that are submitted later than
the one week grace period after the grades are posted on blackboard. You
are responsible for checking your posted grades in a timely manner.
You may help each other understand how to use the CETS computers and course
Each student is expected to do his/her own work -- including developing the
details, drawing circuits, performing simulations, and writing the
solutions. For the homeworks and projects, you are free to
discuss basic strategies and approaches with your fellow classmates or
others, but detail designs, implementations, analysis, and writeups should
always be the work of the individual. If you get advice or insights from
others that influenced your work in any way, please acknowledge this in
In general, you are expected to abide by Penn's
Code of Academic Integrity. If there is any uncertainty, please ask.