ESE370 Fall 2013 Working Schedule

Wk Lect. Date Lecture Slides Due Ref.
1 1 8/28 W Intro/Overview [ppt] [pdf] 1 through 1.2; review course web page completely
2 8/30 F Transistor Introduction (basics) and Diagnostic Quiz [ppt] [pdf] review ESE215
2 9/2 M Labor Day
3 9/4 W Gates from Transistors [ppt] [pdf] 6.2 through static properites in 6.2.1
9/5 R HW1
4 9/6 F Lab (Detkin): Gate from Discrete Transistors Lab Instructions HW2
lab instructions
3 5 9/9 M Transistor Introduction (first order) [ppt] [pdf] 3.1
6 9/11 W Restoration [ppt] [pdf] 1.3.2
9/12 R HW2
7 9/13 F Lab (Ketterer): SPICE starter B
HW2 all
4 8 9/16 M Delay and RC Response [ppt] [pdf]
ADD DATE
1.3.3
9 9/18 W MOS Model [ppt] [pdf] 2.1--2.3, 3.3.1
9/19 R HW3
10 9/20 F MOS Transistor Operating Regions: Part I [ppt] [pdf] 3.3.2 (to 94)
5 11 9/23 M MOS Transistor Operating Regions: Part II [ppt] [pdf] 3.3.2 (to 103)
12 9/25 W MOS Transistor Details [ppt] [pdf] 3.3.2 (remainder)
9/26 R HW4
13 9/27 F MOS Variation [ppt] [pdf] 3.3.3, 3.4
6 9/30 M Midterm 7--9pm in Towne 309 (no lecture) exam (no answers) solutions
14 10/2 W Layout and Area [ppt] [pdf] 2.3, A
15 10/4 F MOS Scaling [ppt] [pdf] DROP DATE 3.5
7 16 10/7 M Performance: Inverter [ppt] [pdf] 5.4
10/8 T HW5
17 10/9 W Performance: Gates [ppt] [pdf] 6.2.1 Delay and Performance Sections
10/11 F Fall Break
8 18 10/14 M Energy Basics [ppt] [pdf] 5.5
19 10/16 W Energy and Power (short circuit, optimizing) [ppt] [pdf] 6.2.1 Power Consumption
10/17 R HW6
20 10/18 F Ratioed Gates [ppt] [pdf] 6.2.2
9 21 10/21 M Design Space Exploration [ppt] [pdf]
22 10/23 W Pass-Transistor Logic: Part 1 [ppt] [pdf] 6.2.3
10/24 R Proj1.M
23 10/25 F Pass-Transistor Logic: Part 2 (cascading without buffers)
[ppt] [pdf] 6.2.3
10 24 10/28 M Distributed RC Wire and Elmore Delay [ppt] [pdf] (4 to 4.3), 4.4, 4.5.1
25 10/30 W Lumped RC Interconnect and Driving Capacitive Loads [ppt] [pdf] 5.4.3
10/31 R Proj1
26 11/1 F Synchronous Timing Discipline and Clocking [ppt] [pdf] 7.1--7.3
11 11/4 M Midterm 7--9pm in Towne 309 (no lecture) [exam no solutions] solutions
27 11/6 W Clocked Logic (More Synchronous, Precharge Logic) [ppt] [pdf] 7.5
28 11/8 F Memory overview, organization, and architecture [ppt] [pdf] Withdraw DATE 12.1
12 29 11/11 M RAM: Core Part 1 [ppt] [pdf] 12.2.3
11/12 T HW7
30 11/13 W RAM: Core Part 2 [ppt] [pdf] 12.2.3
31 11/15 F RAM: periphery [ppt] [pdf] 12.3
13 32 11/18 M Lab (Detkin): Inductive Noise and crosstalk Lab Instructions 2.4
11/19 T Proj2.M
33 11/20 W Crosstalk [ppt] [pdf] 9.2.1
34 11/22 F Lab (Detkin): Transmission Line Measurement Lab Instructions
14 35 11/25 M Noise: Inductive [ppt] [pdf] 9.4, 4.3.3
11/26 T Penn says this is logical a "Thursday" :-) Proj2
36 11/27 W Trans. Line Intro and Analysis [ppt] [pdf] 4.4.5, 4.5.2, 9.4.2
11/29 F Thanksgiving Holiday
15 37 12/2 M Trans. Line Modeling and Termination [ppt] [pdf]
38 12/4 W Transmission Lines Implications [ppt] [pdf] Bakoglu 6.1 (6.11)
12/5 R HW8
39 12/6 F Repeaters in Wiring
[ppt] [pdf] 9.3.3
16 40 12/9 M Review (Spencer)
12/13 F Final Exam 12pm noon -- location Towne 307 [final] [solutions]

This working calendar is on the web: http://www.seas.upenn.edu/~ese370/fall2013/syllabus.html. Please, recheck the page on the web as details may be adjusted as the term progresses. Lectures notes, reading, and handouts will be filled as we reach them.


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