ESE370 Fall 2014 Working Schedule

Wk Lect. Date Lecture Slides Due Ref.
1 1 8/27 W Intro/Overview [ppt] [pdf] 1 through 1.2; review course web page completely
2 8/29 F Transistor Introduction (basics) and Diagnostic Quiz [ppt] [pdf] review ESE215
2 9/1 M Labor Day
3 9/3 W Gates from Transistors [ppt] [pdf] 6.2 through static properites in 6.2.1
9/4 R HW1
4 9/5 F Lab (Detkin): Gate from Discrete Transistors Lab Instructions HW2
lab instructions
3 5 9/8 M Transistor Introduction (first order) [ppt] [pdf] 3.1
6 9/10 W Restoration [ppt] [pdf] 1.3.2
9/111 R HW2
7 9/12 F Lab (Ketterer): SPICE starter B
HW3 all
4 8 9/15 M Delay and RC Response [ppt] [pdf]
ADD DATE
1.3.3
9 9/17 W MOS Model [ppt] [pdf] 2.1--2.3, 3.3.1
9/18 R HW3
10 9/19 F MOS Transistor Operating Regions: Part I [ppt] [pdf] 3.3.2 (to 94)
5 11 9/22 M MOS Transistor Operating Regions: Part II [ppt] [pdf] 3.3.2 (to 103)
12 9/24 W MOS Transistor Details [ppt] [pdf] 3.3.2 (remainder)
9/25 R HW4
13 9/26 F MOS Variation [ppt] [pdf] 3.3.3, 3.4
6 9/29 M Midterm 7--9pm in Towne 303 (no lecture) exam (no answers) solutions
14 10/1 W Layout and Area [ppt] [pdf] 2.3, A
15 10/3 F MOS Scaling [ppt] [pdf] DROP DATE 3.5
7 16 10/6 M Performance: Inverter [ppt] [pdf] 5.4
10/7 T HW5
17 10/8 W Performance: Gates [ppt] [pdf] 6.2.1 Delay and Performance Sections
10/10 F Fall Break
8 18 10/13 M Energy Basics [ppt] [pdf] 5.5
19 10/15 W Energy and Power (short circuit, optimizing) [ppt] [pdf] 6.2.1 Power Consumption
10/16 R HW6
20 10/17 F Ratioed Gates [ppt] [pdf] 6.2.2
9 21 10/20 M Design Space Exploration [ppt] [pdf]
22 10/22 W Pass-Transistor Logic: Part 1 [ppt] [pdf] 6.2.3
10/23 R Proj1.M
23 10/24 F Pass-Transistor Logic: Part 2 (cascading without buffers)
[ppt] [pdf] 6.2.3
10 24 10/27 M Distributed RC Wire and Elmore Delay [ppt] [pdf] (4 to 4.3), 4.4, 4.5.1
25 10/29 W Driving Capacitive Loads [ppt] [pdf] 5.4.3
10/30 R Proj1
26 10/31 F Synchronous Timing Discipline and Clocking [ppt] [pdf] 7.1--7.3
11 11/3 M Midterm 7--9pm in Towne 311 (no lecture) [exam no solutions] solutions
27 11/5 W Clocked Logic (More Synchronous, Precharge Logic) [ppt] [pdf] 7.5
28 11/7 F Memory overview, organization, and architecture [ppt] [pdf] Withdraw DATE 12.1
12 29 11/10 M RAM: Core Part 1 [ppt] [pdf] 12.2.3
11/11 T HW7
30 11/12 W RAM: Core Part 2 [ppt] [pdf] 12.2.3
31 11/14 F RAM: periphery [ppt] [pdf] 12.3
13 32 11/17 M Lab (Detkin): Inductive Noise and crosstalk Lab Instructions 2.4
11/18 T Proj2.M
33 11/19 W Crosstalk [ppt] [pdf] 9.2.1
34 11/21 F Lab (Detkin): Transmission Line Measurement Lab Instructions
14 35 11/24 M Noise: Inductive [ppt] [pdf] 9.4, 4.3.3
11/25 T Penn says this is logical a "Thursday" :-) Proj2
36 11/26 W Trans. Line Intro and Analysis [ppt] [pdf] 4.4.5, 4.5.2, 9.4.2
11/28 F Thanksgiving Holiday
15 37 12/1 M Trans. Line Modeling and Termination [ppt] [pdf]
38 12/3 W Transmission Lines Implications [ppt] [pdf] Bakoglu 6.1 (6.11)
12/4 R HW8
39 12/5 F Repeaters in Wiring
[ppt] [pdf] 9.3.3
16 40 12/8 M Review
12/18 R Final Exam noon-2pm, Towne 303 [final] [solutions]

This working calendar is on the web: http://www.seas.upenn.edu/~ese370/fall2014/syllabus.html. Please, recheck the page on the web as details may be adjusted as the term progresses. Lectures notes, reading, and handouts will be filled as we reach them.


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