ESE370 Fall 2015 Working Schedule

Wk Lect. Date Lecture Slides Due Reading
1 1 8/26 W Intro/Overview [lec1] [lec1_6up] 1 through 1.2; review course web page completely
2 8/28 F Transistor Introduction (basics) and Gates from Transistors [lec2] [lec2_6up] review ESE215; 6.2 through static properties in 6.2.1
2 8/31 M Lab (Detkin): Gate from Discrete Transistors [Lab Instructions] Diagnostics Quiz (Online in Canvas) HW 2; lab instructions
3 9/2 W Gates from Transistors (concl) and Transistor Introduction (first order) [lec3] [lec3_6up] HW 1 3.1
4 9/4 F Regenerative Property [lec4] [lec4_6up] 1.3.2
3 9/7 M Labor Day
9/9 W Lab (Detkin): SPICE starter HW 2 HW 3
5 9/11 F Delay and RC Response [lec5] [lec5_6up] 1.3.3
4 6 9/14 M MOS Model [lec6] [lec6_6up]
ADD DATE
2.1-2.3, 3.3.1
7 9/16 W MOS Transistor Operating Regions: Part 1 [lec7] [lec7_6up] [lec7_PNJunction] HW 3 3.3.2 (to pg 94)
8 9/18 F MOS Transistor Operating Regions: Part 2 [lec8] [lec8_6up] 3.3.2 (to pg 103)
5 9 9/21 M MOS Transistor Details [lec9] [lec9_6up] 3.3.2 (remainder)
10 9/23 W MOS Transistor Variation [lec10] [lec10_6up] HW 4 3.3.3, 3.4
9/25 F Pope Visit (no lecture)
6 9/28 M Midterm 1: 7--9pm in Moore 216 (no lecture) exam (no answers) solutions
11 9/30 W Layout and Area [lec11] [lec11_6up] 2.3
12 10/2 F MOS Scaling [lec12] [lec12_6up] DROP DATE 3.5
7 13 10/5 M Performance: Inverter [lec13] [lec13_6up] 5.4
14 10/7 W Performance: Gates [lec14] [lec14_6up] HW 5 6.2.1 Delay and Performance Sections
10/9 F Fall Break
8 15 10/12 M Energy Basics [lec15] [lec15_6up] 5.5
16 10/14 W Energy and Power (short circuit, optimizing) [lec16] [lec16_6up] HW 6 6.2.1 Power Consumption
17 10/16 F Ratioed Gates [lec17] [lec17_6up] 6.2.2
9 18 10/19 M Design Space Exploration [lec18] [lec18_6up] [lec18_design_ex]
19 10/21 W Pass-Transistor Logic: Part 1 [lec19] [lec19_6up] Proj 1.M 6.2.3
20 10/23 F Pass-Transistor Logic: Part 2 (cascading without buffers)
[lec20] [lec20_6up] 6.2.3
10 21 10/26 M Distributed RC Wire Elmore Delay [lec21] [lec21_6up] (4 to 4.3), 4.4, 4.5.1
22 10/28 W Driving Capacitive Loads [lec22] [lec22_6up] Proj 1 5.4.3
23 10/30 F Synchronous Timing Discipline and Clocking [lec23] [lec23_6up] 7.1--7.3
11 11/2 M Clocked Logic (More Synchronous, Precharge Logic) [lec24] [lec24_6up] 7.5
24 11/4 W Midterm 2: 7--9pm in Moore 216 (no lecture) [exam no solutions] solutions
25 11/6 F Memory overview, organization, and architecture [lec25] [lec25_6up] Withdraw DATE 12.1
12 26 11/9 M RAM: Core Part 1 [lec26] [lec26_6up] 12.2.3
27 11/11 W RAM: Core Part 2 [lec27] [lec27_6up] HW 7 12.2.3
28 11/13 F RAM: periphery [lec28] [lec28_6up] 12.3
13 11/16 M Lab (Detkin): Inductive Noise and crosstalk [Lab Instructions] 2.4
29 11/18 W Crosstalk [lec29] [lec29_6up] 9.2.1
11/20 F Lab (Detkin): Transmission Line Measurement Lab Instructions
14 30 11/23 M Noise: Inductive [lec30] [lec30_6up] HW 8 9.4, 4.3.3
31 11/25 W('F') Trans. Line Intro and Analysis [lec31] [lec31_6up] Proj 2.M 4.4.5, 4.5.2, 9.4.2
11/27 F Thanksgiving Holiday
15 32 11/30 M Trans. Line Modeling and Termination [lec32] [lec32_6up] 4.4.5, 4.5.2, 9.4.2
33 12/2 W Transmission Lines Implications [lec33] [lec33_6up] Bakoglu 6.1 (6.11)
34 12/4 F Repeaters in Wiring
[lec34] [lec34_6up] [Big Ideas] [Big Ideas_6up] Proj 2 9.3.3
16 35 12/7 M Review
EW 12/15 T Final Exam noon-2pm in Towne 311 [final] [solutions]

This working calendar is on the web: http://www.seas.upenn.edu/~ese370/fall2015/syllabus.html. Please, recheck the page on the web as details may be adjusted as the term progresses. Lectures notes, reading, and handouts will be filled as we reach them.


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