Circuit-Level Modeling, Design, and Optimization for Digital Systems

Course: ESE370

Units: 1.0 CU
Terms: Fall
When: MWF 12-1pm
Where: Towne 307
Instructor: Tania Khanna (Moore 201Q, seas: taniak) (office hours: W 1-3pm or by appointment)
TA: Angelina Risi (seas: risi) (office hours: T 6-8pm, F 10am-12pm location: Towne 211)
Prerequisites: ESE 150, ESE 215, CIS 240 is also highly recommended. Roundup of topics you should be familiar with.
URL: <http://www.seas.upenn.edu/~ese370/>

Quick Links: [Course Objectives] [Grading] [Policies] [Fall 2018 Calendar] [Reading] [Piazza] [Tool Guides]

Catalog Level Description: Circuit-level design and modeling of gates, storage, and interconnect. Emphasis on understanding physical aspects which drive energy, delay, area, and noise in digital circuits. Impact of physical effects on design and achievable performance.

Role and Objectives

The goal of this course is to teach students what they need to know about the physical aspects (area, delay, energy, noise) of electronic circuits to support high-speed, low-energy, area-efficient design of robust digital and computer systems. Students will learn:

disciplines for robust digital logic and signaling (e.g., restoration, clocking, handshaking)
where delay, energy, area, and noise arises in gates, memory, and interconnect
how to model these physical effects both for back-of-the-envelope design (e.g. RC and Elmore delay) and detailed simulation (e.g., SPICE)
the nature of tradeoffs in optimization
how to design and optimize logic, memory, and interconnect structures at the gate, transistor, and wire level
how technology scales and its impact on digital circuits and computer systems

This course comes after a basic introduction to devices and circuits (ESE215) and a course on gate-level digital design (ESE150/CIS240). It should serve both students who will go on to do circuit-level design and those who will work primarily at higher levels and need to be able to reason about technology and fundamental limits to establish capabilities and understand the circuit-level impact of optimizations they perform at higher levels of design. This will be the most detailed class on physical issues required for CMPE BSE students. Students may choose to continue with more advanced circuit and VLSI courses (e.g., ESE570).

Rough Syllabus (by weeks)

Review transistor, introduce MOS model
Gates and restoration, basic gate delay, review transient response
MOS Transistors (models with physical device parameters (W,L,N_a...)), scaling, variation
Energy, Delay, Area implications and tradeoffs for MOS circuits
Clocking, latches, flip-flops (setup, hold, clock skew)
Other gate models (ratioed, pre/post-charge)
RC Wire delay and Elmore delay (fanout, transistor sizing)
Wire Effects (buffering, capacitive coupling/crosstalk)
RAM design
Noise: inductive coupling, ground bounce, ionizing particles, thermal noise
Transmission lines
High speed chip-to-chip signaling
Energy and entropy

See Fall 2018 course calendar for day-by-day calendar with assignments.

Text

Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. Digital Integrated Circuits, A Design Perspective, 2nd edition, Prentice Hall, 2003.
Errata for text

Software Tool Guides

Grading

Grading is based on weekly assignments, exams, and a longer end-of-term assignments.

Weekly Assignments [25%]
Projects [30%]
Midterms [20%]
Final [25%]

Projects: Two two-week (minimum) design/optimization projects: (1) transistor design and optimization for logic/gates and (2) memory design.

Policies

Homework Turnin

Homework will be due on Wednesdays (and some Mondays on select weeks) at midnight that day. Assignments must be turned in online via Canvas. Hand written assignments will be accepted, but when specified computer generated figures, graphs and results must be submitted. Homeworks must be legible and all work should be shown. Illegible submissions will not be graded.

Late Assignments

Late assignments will not be accepted or graded. For extenuating circumstances, contact the instructor prior to the due date.

If assignments or exams fall due on a religious holiday, please make arrangements with the instructor to accommodate before the posted due date.

Absentees

Use the Penn Course Absence Report (CAR) in Penn-in-Touch to report absences.

Grade Adjustment

Regrade requests must be submitted to the TA no later than 1 week after the assignment is returned (or grades are posted) to the students. A cover sheet detailing the discrepency should be attached to the original homework, and the TA reserves the right to regrade the entire assignment. Students are responsible for checking posted grades in a timely manner.

Collaboration

You may help each other understand how to use the CETS computers and course CAD tools.

Each student is expected to do his/her own work -- including developing the details, drawing circuits, performing simulations, and writing the solutions. For the homeworks and projects, you are free to discuss basic strategies and approaches with your fellow classmates or others, but detail designs, implementations, analysis, and writeups should always be the work of the individual. If you get advice or insights from others that influenced your work in any way, please acknowledge this in your writeups.

In general, you are expected to abide by Penn's Code of Academic Integrity. If there is any uncertainty, please ask.