System-on-a-Chip Architecture

Course: ESE532

Units: 1.0 CU
Terms: Spring 2017 (first offering)
When: MW 3--4:30pm
Where: Towne 303
Instructor: DeHon (office hours T4:15pm-5:30pm, Levine 270)
TA: Hans Giesen (Lab Hours Tuesday, Thursday 6-7pm, Ketterer)
Prerequisite:
Undergraduate CIS240, ESE350
Graduateworking knowledge of C

URL: <http://www.seas.upenn.edu/~ese532/>

Quick Links: [Course Objectives] [Project] [Grading] [Syllabus] [Course Policies] [Documentation] [piazza] [Relation to other courses]


Catalog Level Description:

Motivation, design, programming, optimization, and use of modern System-on-a-Chip (SoC) architectures. Hands-on coverage of the breadth of computer engineering within the context of SoC platforms from gates to application software, including on-chip memories and communication networks, I/O interfacing, RTL design of accelerators, processors, concurrency, firmware and OS/infrastructure software. Formulating parallel decompositions, hardware and software solutions, hardware/software tradeoffs, and hardware/software codesign. Attention to real-time requirements.


Course Objectives

By the end of theh course, you will be able to:


Topics

Architectural building blocks and heterogeneous architecture, Hardware-Software Codesign, Embedded Software, Interfacing, Computational requirements and system analysis, Concurrency, Real Time, Design-space formulation and exploration, Costs and metrics (energy, area, runtime, reliability, predictability), Quantitative design and analysis.


Rough Syllabus Plan

  1. Overview, scope, methodology
  2. Metrics and bottlenecks
  3. Computational models
  4. Data parallel microarchitectures (SIMD, Vector, GPU)
  5. Thread-level Parallelism and virtualization
  6. Real-time, reactive
  7. Spatial computations, basic mapping from high-level
  8. Fine-grained parallelism microarchitectures (FSMD, VLIW)
  9. High-level synthesis (C-to-gates, resource selection and provisioning)
  10. On-chip networking / Network-on-Chip
  11. VLSI technology and scaling
  12. Memory
  13. Defect and fault tolerance

Detailed 2017 Syllabus.


Project

This course will include a substantial project running throughout term. Students work in groups of 2. Platform will be an SoC-FPGA (e.g., Xilinx Zynq or Intel/Altera Arria), allowing the provisioning of soft-core processors, accelerators, and memory in addition to the use of the embedded SoC logic. It will start with a significant task (like video acquisition, processing, compression, networking). Course starts by running the task on single processor and identify resource requirements. Then, it will deal with I/O for task. It then migrates the task to multiple processors to accelerate. After ther, it develops custom accelerators for task and integrate with networked processor. The final half of the course is an open-ended optimization project using the techniques and design options introduced in the course.


Grading

Grading is based on:


Policies

Writeups

Writeups must be done in electronic form and submitted through Canvas (below). Use CAD or drawing tools where appropriate. Handwritten assignments and hand-drawn figures are not acceptable.

Each individual should turn in a homework or project writeup. The specific homework assignments will specify what portion of the writeup can be performed jointly and what part should be individual. Even if the entire assignment is done jointly, we will still expect individual submissions (both students submit identical PDFs, if it is appropriate for that project or homework assignment).

Homework Turnin

All assignments will be turned in electronically through the Penn Canvas website. Log in to canvas with your PennKey and password, then select ESE 532 from the Courses and Groups dropdown menu. Select Assignments from the links on the left and select the assignment you wish to submit for. Submission should be as a single file (preferably .pdf).

Late Assignments

Assignments must be turned in by the published due date to receive credit.

We will grant each student 3 free late days for the course of the entire term. That means you could, for example, turn in three assignments one day late each or one assignment 3 days late and still receive full credit. The quantum for free late days is a day, so you cannot turn in every assignment 6 hours late and receive full credit.

Collaboration

Students are allowed and encouraged to help each other with the Xilinx tools (SDSoC, SDK, Vivado, Vivado HLS, Windows, Linux) used for the course, but are disallowed from developing collaborative design solutions (C-code, pragmas, design and analysis) outside of identified project groups. Within a project group, the assignment will specify what part should be done as a group and what part should be done individually.

In general, you are expected to abide by Penn's Code of Academic Integrity. If there is any uncertainty, please ask.

Absentees

Use the Penn Course Absence Report (CAR) in Penn-in-Touch to report absences.

Credit Adjustment

Make sure you call any problems with grading to our attention immediately and not later than the next class meeting after they are returned or posted on canvas. To submit a request for a review of a credit assignment on a lab assignment send an email to the instructor stating the nature of the problem and the remedy you desire. We will not consider any requests for grade adjustments that are submitted later than the one week grace period after the grades are posted on canvas. You are responsible for checking your posted grades in a timely manner.

Documentation


Comparison to ESE534

This will borrow or inherit about 1/3 of the material from the
current ESE534. This course will not go deep into how to design a spatial substrate (compute, interconnect), nor go deep into processor--FPGA continuum and instruction design. If offered again, ESE534 will likely evolve to take this course as a pre-requisite. Possibly ESE534 and 535 will merge into a single advanced, follow-on course. Note that ESE534 did not have the kind of hands-on project that becomes a key component of this course.

Comparison to CIS501

This course is complementary to CIS501. This course is more focused on custom, application-oriented design with real-time concerns, while CIS501 focuses on ISA compatibility and best-effort designs. This course assumes you are willing to recompile and perhaps rewrite your application code; as a result, it does not touch upon the ISA abstraction and compatibility and will have almost nothing on dynamic ILP and pipelining of a general-purpose processor. This course will be driven more by real-time concerns rather than best-effort tasks, whereas CIS501 is more focused on best-effort. This course will spend one day on the high-level benefits of memory hierarchy, but will not dive deep into cache-design and cache-hierarchies, which is a major component of CIS501. This course will mostly look at non-shared memory models and architectures with, at most, a small nod to the existence and challenges in shared memory, whereas CIS501 is mostly focused on shared-memory models and architectures.
Last modified: Mon Mar 20 08:25:06 EDT 2017