Reading

• Day 1: January 8, 2007
  • Reccommended: none
  • Supplemental: none
• Day 2: January 10, 2007
  • Reccommended: none
  • Supplemental:
    1. David A. Patterson and John L. Hennessy. Computer Organization and Design, third edition, 2004, Morgan-Kaufmann. Appendix B: The Basics of Logic Design.
• Day 3: January 17, 2007
  • Reccommended: F. Thomson Leighton. Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes, 1992, Morgan-Kaufmann. pp. 32--42.
  • Supplemental:
    1. David A. Patterson and John L. Hennessy. Computer Organization and Design, third edition, 2004, Morgan-Kaufmann. Chapter 3: Arithmetic for Computers.
    2. Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, and André DeHon. Pipelining Saturated Accumulation. In Proceedings of the International Conference on Field-Programmable Technology, December, 2005.
    3. J. Sklansky, Conditional-Sum Addition Logic. IRE Transactions of Electronic Computers, EC-9:226--231, June, 1960.
    4. Richard P. Brent and H. T. Kung, A Regular Layout for Parallel Adders. In IEEE Transactions on Computers, 31(3):260--264, March 1982.
• Day 4: January 22, 2007
  • Reccommended: none
  • Supplemental:
    1. Stephen A. Ward and Robert H. Halstead, Jr., Computation Structures, 1990, MIT Press. Chapter 8: Performance Measures and Tradeoffs
• Day 5: January 24, 2007
  • Reccommended: none
  • Supplemental: none
• Day 6: January 29, 2007
  • Reccommended:
    1. Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu, V. Leo Rideout, Ernest Bassous, and Andre R. LeBlanc. Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions. Journal of Solid-State Circuits, 9(5):256--268, October 1974.
       
  • Supplemental:
    1. International Technology Roadmap for Semiconductors particularly, you might scan the 2005 Executive Summary
    2. Bijan Davari, Robert H. Dennard, and Ghavam G. Shahidi. CMOS Scaling for High Performance and Low Power---The Next Ten Years. Proceedings of the IEEE, 83(4):595--606, April 1995.
    3. Mark Bohr. MOS Transistors: Scaling and Performance Trends. Semiconductor International, pages 75--79, June 1995.
    4. Mark Bohr. Interconnect Scaling -- The Real Limiter to High Performance ULSI. In International Electron Devices Meeting 1995 Technical Digest, pages 241--244. Electron Devices Society of IEEE, December 1995.
• Day 7: January 31, 2007
  • Reccommended:
    1. David J. Frank. ``Power-constrained CMOS Scaling Limits,'' IBM Journal of Research and Development, Volume 46, Number 2/3, March/May, 2002.
  • Supplemental:
    1. Richard P. Feynman. Feynman Lectures on Computation. Westview Press, 1999. Chapter 5: Reversible Computation and the Thermodynamics of Computation, pp. 137--184.
    2. Anantha P. Chandrakasan, Samuel Sheng, and Robert W. Brodersen, ``Low-Power CMOS Digital Design,'' in IEEE Journal of Solid State Circuits, 1992, Vol. 27, No. 4, pp. 473--484.
    3. W. C. Athas, J. G. Koller, and L. J. Svensson, ``An Energy-Efficient CMOS Line Driver Using Adiabatic Switching,'' USC/ISI ACMOS-TR-2, July 30, 1993.
    4. S. G. Younis and T. F. Knight, Jr., Asymptotically zero energy split-level charge recovery logic, In International Workshop on Low Power Design, pages 177--182, 1994.
    5. W. C. Athas, J. Svensson, J. G. Koller, N. Tzartzanis and E. Y. Chou. ``Low-power digital systems based on adiabatic-switching principles,'' In IEEE Trans. on VLSI Systems, Vol.2,No.4,pp398--406, Dec 1994.
    6. Thomas Indermaur and Mark Horowitz, Evaluation of Charge Recovery Circuits and Adiabatic Switching for Low Power CMOS Design, Symposium on Low-Power Electronics, October 1994.
    7. Victor Zhirnov, Ralph Cavin, Jim Hutchby, and George Bourianoff, ``Limits to binary logic switch scaling - a gedanken model,'' Proceedings of the IEEE, Volume 91, Number 11, pp. 1934--1939, November, 2003.
    8. Craig S Lent, Mo Liu and Yuhui Lu, ``Bennett clocking of quantum-dot cellular automata and the limits to binary logic scaling'', Nanotechnology, Volume 17, Issue 16, pp. 4240-4251, August 2006.
• Day 8 and 9: February 5 and 7, 2007
  • Reccommended:
    André DeHon. Reconfigurable Architectures for General-Purpose Computing. AI Technical Report 1586, MIT Artificial Intelligence Laboratory, 545 Technology Sq., Cambridge, MA 02139, September 1996. [abstract and pointers]. Chapter 8: Instructions and Chapter 9: Instruction Architecture Space.
  • Supplemental: none
• Day 10: February 12, 2007
  • Reccommended:
    1. André DeHon. Comparing Computing Machines. In Configurable Computing: Technology and Applications, Proceedings of SPIE 3526, p. 124, November 1998. [abstract, paper, and slide links]
  • Supplemental:
    1. Ian Kuon and Jonathan Rose. Measuring the Gap Between FPGAs and ASICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(2):203--215, February 2007.
• Day 11: February 14, 2007
  • Reccommended:
    1. Jonathan Rose, Robert Francis, David Lewis, and Paul Chow. Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency. IEEE Journal of Solid-State Circuits, 25(5):1217--1225, October 1990.
  • Supplemental:
    1. André DeHon, Reconfigurable Architectures for General-Purpose Computing. AI Technical Report 1586, MIT Artificial Intelligence Laboratory, 545 Technology Sq., Cambridge, MA 02139, pages 35-41, October 1996. [PS for pp. 35-41], [HTML for Chapter 4], [Full Document Pointers].
    2. S. Singh, Jonathan Rose, Paul Chow, and David Lewis. The Effect of Logic Block Architecture on FPGA Performance. IEEE Journal of Solid-State Circuits, 27(3):281--287, March 1992.
    3. Chuck Hastings, When is a Memory Not a Memory, In Proceedings of the Electro/87 Mini/Micro Northeast, page 1132 ff. (4/5/1-18), 1987.
    4. Stephen D. Brown, Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. Field-Programmable Gate Arrays. Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts, 02061 USA, 1992.
• Day 12: February 21, 2007
  • Recommended:
    1. none
  • Supplemental:
    1. Jack Kouloheris and Abbas El Gamal. PLA-based FPGA Area versus Cell Granularity. In Proceedings of the Custom Integrated Circuits Conference, pages 4.3.1--4. IEEE, May 1992.
    2. Kevin Chung, Satwant Singh, Jonathan Rose, and Paul Chow. Using Hiearchical Logic Blocks to improve the Speed of FPGAs. In FPGAs, Will Moore and Wayne Luk, eds. (proceedings of the Oxford 1991 International Workshop on Field Programmable Logic and Applications), pp. 102--113.
    3. Kevin Chung and Jonathan Rose. TEMPT: Technology Mapping for Exploration of FPGA Architectures with Hard-Wired Connections. In Proc. 29th ACM/IEEE Design Automation Conference, June 1992, Anaheim, CA, pp. 361-367.
    4. Soon Ong Seo, A High Speed Field-Programmable Gate Array Using Programmable Minitiles, University of Toronto Master's Thesis, 1994.
    5. Altera. Stratix III FPGA Family Data Sheet.
    6. Xilinx. Virtex 5 Data Sheet and User's Guide
• Day 13: February 26, 2007
  • Reccommended:
    1. Charles E. Leiserson, VLSI Theory and Parallel Supercomputing, 1989 Caltech Decennial VLSI Conference. Also MIT/LCS/TM 402.
  • Supplemental:
    1. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, pages 416-421. Addison Wesley Publishing Company, 1990.
• Day 14: February 28, 2007
  • Reccommended:
    1. B. S. Landman and R. L. Russo. On Pin Versus Block Relationship for Partitions of Logic Circuits. IEEE Transactions on Computers, 20(12):1469--1479, 1971. (n.b. This is the classic paper showing empirical evidence for Rent's Rule.)
  • Supplemental:
    1. Abbas El Gamal. Two-Dimensional Stochastic Model for Interconnections in Master Slice Integrated Circuits. IEEE Transactions on Circuits and Systems, 28(2):127--138, February 1981. (n.b. The math gets a bit heavy. Read this for the key results and don't sweat the more technical portions unless you really want.)
    2. W. R. Heller, C. George Hsi, Wadi F. Mikhaill. Wirability---Designing Wiring Space for Chips and Chip Packages. IEEE Design and Test of Computers, pages 43--51, August, 1984.
    3. M. Y. Lanzerotti, G. Fiorenza, and R. A. Rand, Microminiature Packaging and Integrated Circuitry: The Work of E. F. Rent, with an Application to On-Chip Interconnection Requirements, IBM Journal of Research and Development, 49(4/5):777, 2005
• Day 15: March 12, 2007
  • Reccommended:
    1. André DeHon. Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why you don't really want 100% LUT utilization). In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 125--134, February 1999. [abstract,paper, and slide links].
  • Supplemental:
    1. Russell Tessier and Heather Giza. Balancing Logic Utilization and Area Efficiency in FPGAs. In Conference on Field Programmable Logic and Applications (FPL '2000), pages 535--544, August 28--30, 2000.
• Day 16: March 14, 2007
  • Reccommended:
    1. André DeHon. Rent's Rule Based Switching Requirements. In System-Level Interconnect Prediction (SLIP 2001), pages 197--204, March 31--April 1, 2001, [abstract, paper links].
    2. Bruce Maggs. ``Randomly wired multistage networks,'' in Statistical Science, volume 8, number 1, February, 1993, pp. 70--75.
  • Supplemental:
    1. Sandeep Bhatt and Frank Thomson Leighton. A Framework for Solving VLSI Graph Layout Problems. In Journal of Computer System Sciences v28p300-343, 1984.
    2. André DeHon. Entropy, Counting, and Programmable Interconnect. (Short version in FPGA'96). [HTML version with extended appendix] n.b. The switching requirements for the m choose k switching block is detailed in the appendix of the TR version.
    3. Aditya A. Agarwal and David Lewis. Routing Architectures for Hierarchical Field Programmable Gate Arrays. In Proceedings 1994 IEEE International Conference on Computer Design, pages 475--478. IEEE, October 1994.
    4. Vi Cuong Chan and David M. Lewis. Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays. In Proceedings of the 1996 International Symposium on Field-Programmable Gate Arrays, pages 51--57. ACM/SIGDA, February, 1996.
    5. Ronald I. Greenberg and Charles E. Leiserson. A Compact Layout for the Three-Dimensional Tree of Meshes. In Applied Math Letters v1n2p171--176, 1988.
    6. André DeHon. Compact, Multilayer Layout for Butterfly Fat-Tree. In Twelfth Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA 2000), pages 206--215, July 9-12, 2000. [abstract, paper links].
    7. Sanjeev Arora, F. Thomson Leighton, and Bruce M. Maggs. ``On-line Algorithms for Path Selection in a Nonblocking Network,'' SIAM Journal on Computing, Volume 25, Number 3, June 1996, pp. 600-625.
• Day 17: March 19, 2007
  • Reccommended: none?
  • Supplemental:
    1. Jonathan Rose and Stephen Brown. The Effect of Switch Box Flexibility on Routability of Field Programmable Gate Arrays. In Proceedings of the 1990 Custom Integrated Circuits Conference, p. 27.5.1--4, 1990.
    2. Yu-Liang Wu, Shuji Tsukiyama, and Malgorzata Marek-Sadowska, Graph Based Analysis of 2-D FPGA Routing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(1):33--44, January 1996.
    3. Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, and Shiji Tsukiyama, Not Necessarily More Switches More Routability. In Proceesings of the 1996 Asia Pacific Design Automation Conference, 1996.
    4. Jonathan Rose and Stephen Brown. Flexibility of Interconnection Structures for Field-Programmable Gate Arrays. IEEE Journal of Solid-State Circuits, 26(3):277--282, March 1991.
    5. Yao-Wen Chang and D. F. Wong and C. K. Wong. Universal Switch-Module Design for Symmetric-Array-Based FPGAs. In Proceedings of the 1996 International Symposium on Field-Programmable Gate Arrays, pages 80--86. ACM/SIGDA, February, 1996.
    6. Vaughn Betz and Jonathan Rose, ``FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density,'' ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 1999, pp. 59 - 68. [PDF]
    7. Vaughn Betz and Jonathan Rose, ``How Much Logic Should Go in an FPGA Logic Block?'', in IEEE Design & Test Magazine, Vol. 15, No. 1, Jan-March 1998, pp. 10-15. [PDF]
    8. Stephen D. Brown, Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. Field-Programmable Gate Arrays. Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts, 02061 USA, 1992.
    9. Vaughn Betz, Jonathan Rose, and Alexander Marquardt. Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, 1999.
    10. Guy Lemieux, Edmund Lee, Marvin Tom, and Anthony Yu, ``Directional and Single-DriverWires in FPGA Interconnect,'' IEEE International Conference on Field-Programmable Technology, December 2004, pp. 41--48.
• Day 18: March 21, 2007
  • Reccommended:
    1. André DeHon and Raphael Rubin. ``Design of FPGA Interconnect for Multilevel Metalization,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 12, Number 10, Pages 1038--1050, October 2004. [abstract and links]
    2. André DeHon. ``Unifying Mesh- and Tree-Based Programmable Interconnect,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 12, Number 10, Pages 1051--1065, October, 2004. [abstract and links]
  • Supplemental:
    1. Frank Thomson Leighton. ``New lower bound techniques for VLSI,'' in Proceedings of the Twenty-Second Annual Symposium on the Foundations of Computer Science, 1981.
• Day 19: March 26, 2007
  • Reccommended:
    1. F. Thomson Leighton. Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes, pp. 102--124. Morgan Kaufmann Publishers, Inc., 1992.
  • Supplemental:
    1. Charles Leiserson, Flavio Rose, and James Saxe. Optimizing Synchronous Circuitry by Retiming. In Third Caltech Conference On VLSI, pp. 87--116. March 1993.
    2. Charles Leiserson and James Saxe. Optimizing Synchronous Systems. Journal of VLSI and Computer Systems, 1(1), pp. 41--67.
• Day 20: March 28, 2007
  • Reccommended:
    1. Andrew S. Huang and John P. Shen. ``A Limit Study of Local Memory Requirements Using Value Reuse Profiles'', in Proceedings of MICRO-28, pp. 71--81, December, 1995.
  • Supplemental:
    1. William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, Varghese George, John Wawrzynek, André DeHon. HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 69--78, February 1999. [abstract, paper, and slide links].
• Day 21: April 1, 2007
  • Reccommended:
    1. André DeHon. Multicontext Field-Programmable Gate Arrays. 1997. [PS]
  • Supplemental:
    1. Steve Trimberger, Dean Carberry, Anders Johnson, and Jennifer Wong. A Time Multiplexed FPGA. In Proceedings of the 1997 International Symposium on Field-Programmable Custom Computing Machines. April, 1997.
• Day 22: April 4, 2007
  • Reccommended:
    1. William J. Dally and Brian Towles, Route Packets, Not Wires: On-Chip Interconnection Networks. In Proceedings of the Design Automation Conference, pp. 684-689, 2001.
    2. Nachiket Kapre, Nikil Mehta, Michael deLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael Wrighton, and André DeHon. Packet-Switched vs. Time-Multiplexed FPGA Overlay Networks. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 2006.
  • Supplemental:
    1. Charles Seitz, Let's Route Packets Instead of Wires. In Proceedings of the 6th MIT Conference on Advanced Research in VLSI, pp. 133--137, 1990. [online link?]
    2. Jose Duato, Sudhakar Yalamanchili, and Lionel Ni, Interconnection Networks, Morgan Kaufmann, 2002.
    3. William Dally and Brian Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004.
    4. Andre DeHon, Frederic Chong, Matthew Becker, Eran Egozy, Henry Minsky, Samuel Peretz, and Thomas F. Knight, Jr. METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks. In Proceedings of the International Symposium on Computer Architecture, pages 266-277, May 1994.
• Day 23: April 9, 2007
  • Reccommended: none
  • Supplemental:
    1. André DeHon, Reconfigurable Architectures for General-Purpose Computing. AI Technical Report 1586, MIT Artificial Intelligence Laboratory, 545 Technology Sq., Cambridge, MA 02139, pages 182--204, October 1996. [PS for pp. 182--204], [HTML for Chapter 10], [Full Document Pointers].
• Day 24: April 11, 2007
  • Reccommended:
    1. Daniel J. Magenheimer, Liz Peters, Karl Pettis, and Dan Zuras. ``Integer Multiplication and Division on the HP Precision Architecture'', in Proceedings of the Second International Conference on the Architectural Support for Programming Languages and Operating Systems, pp. 90--99 (1987).
    2. Kenneth David Chapman, ``Fast Integer Multipliers fit in FPGAs'', in Electronic Design News. Vol. 30, number 10, May 12, 1993. [ Anonymous FTP www.ednmag.com:EDN/di_sig/DI1223Z.ZIP].
  • Supplemental:
    1. André DeHon. ``Sepcialization versus Configuration''. Transit Note 113. January, 1995 [HTML]
    2. M. J. Wirthlin, B. L. Hutchings. ``Improving Functional Density Through Run-Time Constant Propagation'', in ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 86-92 (1997). [PS]
    3. John Villasenor, Brian Schoner, Kang-Ngee Chia, and Charles Zapata, ``Configurable Computer Solutions for Automatic Target Recognition'', in Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, April, 1996.
• Day 25: April 16, 2007
  • Reccommended:
    1. André DeHon and Helia Naeimi. Seven Strategies for Tolerating Highly Defective Fabrication. In IEEE Design and Test of Computers, Volume 22, Number 4, Pages 306--315, July-August 2005. [abstract].
    2. David Patterson, Garth Gibson, and Randy Katz, A Case for Redundant Arrays of Inexpensive Disks (RAID). In Proceedings of the ACM SIGMOD Conference, p. 109--116, June 1988.
  • Supplemental:
    1. Bruce Culbertson, Rick Amerson, Richard Carter, Philip Kuekes, and Greg Snider, Defect Tolerance on the Teramac Custom Computer. In IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), pp. 116--123, April, 1997.
    2. André DeHon, Frederic Chong, Matthew Becker, Eran Egozy, Henry Minsky, Samuel Peretz, and Thomas F. Knight, Jr., ``Transit Note #97: METRO: A Building Block for Fault-Tolerant, Multiprocessor Routing Networks,'' [compressed PS]
• Day 26: April 18, 2007
  • Reccommended:
    1. TBD
  • Supplemental:
    1. Brent Keeth and Jacob Baker, DRAM Circuit Design: A Tutorial, IEEE Press, 2001, pp. 108--116.
    2. Ashok K. Sharma, Semiconductor Memories, IEEE Press, 1997, pp. 230--248.