Department of Electrical and Systems Engineering

ESE570: DIGITAL INTEGRATED CIRCUITS AND VLSI FUNDAMENTALS
Spring 2015

Professor Kenneth R. Laker


Do not print copies of this material on the CETS or Detkin Lab printers.


General


Syllabus


Class Notes
Handouts


Policies


Homework
Exams


Project


Links

SPICE


Cadence
VerilogXL Example

 

 

 

 


Description

The course explores the design aspects involved in the realization of CMOS integrated circuits/systems from device up to the register/subsystem level. It addresses major design methodologies with emphasis placed on structured full custom design. The course includes the study of the MOS device, critical interconnect and gate characteristics that determine the performance of VLSI circuits. It also includes CMOS logic design from transistor level schematic to layout for fabrication. Students will use state-of-the art CAD tools to verify designs and develop efficient circuit layouts.
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Course Educational Objectives

A2. Apply the models for state-of-the-art VLSI components, fabrication steps, hierarchical design flow and semiconductor business economics to judge the manufacturability of a design and assess its manufacturing costs.

B1. Design simulated experiments using Cadence to verify the integrity of a CMOS circuit and its layout.

C1. Design digital circuits that are manufacturable in CMOS.

K1. Apply the Cadence VLSI CAD tool suite layout digital circuits for CMOS fabrication and verify said circuits with layout paarasitic elements.

K2, C2. Apply their course knowledge and the Cadence VLSI CAD tools in a team based capstone design project that involves much the same design flow they would encounter in a semiconductor design industrial setting. Capstone project is presented in a formal report due at the end of the semester.

 


General Information

Instructor

Kenneth R. Laker
Room 203 Moore
Phone: 215-898-5340
Email: laker@seas.upenn.edu

Teaching Assistants

TA: Matt Hongjie Zhu (Primary responsility is Cadence)

Email: honzhu@seas.upenn.edu

Grader: Megha Nadig Rathnakara

Email: megn@seas.upenn.edu

Grader: Joonyi Koh

Email: joonyi2011@gmail.com

Grader: Wanqing Xin

Email: xinwanq19@163.com

Time and Location

Tuesday and Thursday, 4:30 to 6:00 PM, Room TOWNE 313

Office Hours

Prof. K. Laker: Mondays; 10:00 AM to 12:00 Noon in 203 Moore, or by appointment.

Matt Hongje Zhu: Mondays: 5:30 to 7:00 PM and Thursdays: 12:00 Noon to 3:00 PM in 307 Moore. or by appointment. NEW

Megha Nadig Rathnakara: Mondays: 11:00 AM to 1:00 PM and Fridays: from 10:30 AM to 12:30 PM in 307 Moore, or by appointment.

Joonyi Koh: Mondays and Wednesdays: 4:30 to 6:30 PM in 307 Moore, or by appointment.

Wanqing Xin: Wednesdays; 1:00-3:00 PM and thursdays: 10:00 AM-12:00 Noon in 307 Moore, or by appointment.

SPECIAL MID-TERM EXM OFFICE HOURS

Prerequisite

ESE370 or equivalent. Undergraduate students need permission of instructor.

Main texts

Reference texts


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2015 Syllabus

No.

TOPIC(s)

TEXT CHAPTERS

No. CLASS PERIODS

1

Introduction

1

1.5

2

Fabrication of MOS Circuits

2

2

3

MOS Transistor Theory

3

3

4

Modeling of MOS Transistors using SPICE

4

1

5

MOS Inverters: Static Characteristics

5

2.5

6

MOS Inverters: SwitchingCharacteristics & Interconnect Effects

6

3

 

 

 

 

7

Combinational MOS Logic Circuits

7

2

 

SPRING BREAK: 09 - 15 Mar15

 

 

 

MID-TERM EXAM: Thurs, 05Mar15 Exam (Postponed to Tuesday, March 17)

NEW MT EXAM COVERAGE: all class and text materials Ch1 to Ch6 and lecture notes material covered in Combinational MOS Logic Circuits up to and including slide 46).

 

1

 

CADENCE TUTORIAL SESSIONS:

See Homework Assignment Section

Sequential MOS Logic Circuits

 

 

8

 

 

 

 

 

2

9

10

Dynamic MOS Logic Circuit

VLSI Design & Implementation Methodologis

9

Class Notes_- Handouts

3

1

11

Semiconductor Memories

10

2

12

Chip Input and Output (I/O) Circuits

13

2

13

Design for Manufacturability

14 (select topics)

1

 

FINAL PROJECT DUE: Thursday, 07May15

 

 

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2015 Mid-Term (05Mar15) Postponed to Tuesday, March 17

2014 Mid-Term (06Mar14)

Grading Policies

Homework: 20 %

Midterm: 40 %

Project: 40 %


Using or attempting to use unauthorized assistance, material, or_ lab results or solutions_ (in part or whole)_ is a violation of theCode of Academic Integrity and will result in a zero grade for the course.
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Homework:Homework assignments will be a combination of textbook problems and CADENCE exercises. Homework is assigned each week by Friday and will be due on Thursday the week after it is assigned._ All homework assignments and due dates will be posted on the ESE 570 website http://www.seas.upenn.edu/~ese570/._ Students are permitted up to THREE one-week latenesses without penalty. That is on three occasions homework may be turned in one week after the official due date._ No other late turn-in of homework will be accepted for any reason._ Homework not turned in accordance with this policy will receive zero grade. Students are expected to manage their three allowed latenesses to allow for unforeseen situations that will result in homework to be turned in late. All homework assignments can now either be submitted at the beginning of class in print, or submitted ahead of class by uploading a pdf file to the appropriate assignment. NEW

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2015 Homework Assignments

2015 Homework Solutions


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2015 PROJECT Materials TBD

·       2015 Project Topic Descriptions TBD

·       2015 Project Protocols, Schedule and Grading Criteria TBD


Useful links


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Class Notes - Handouts

The following handouts are color slide presentations saved in Adobe Acrobat 3.0 Portable Document Format (PDF). They can be viewed using Acrobat Reader 3.0, or higher; or a suitable web browser with an Acrobat PDF Viewer Plug-in, freely distributed by Adobe.._ Adobe Acrobat Reader is freely distributed by Adobe.


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Kenneth R. Laker<laker@ee.upenn.edu>


Created: January 13, 1997; Updated: March 25, 2015 (KRL)