I try to understand and exploit the potential of modern VLSI architectures. I believe we can harness ever-increasing VLSI capacities by organizing our computation spatially on concurrent, parallel architectures such as FPGAs, GPUs, Cells, etc. To truly realize the potential of these exciting architectures, we need to-
develop high-level programming models/frameworks/languages to easily express parallelism in the computation
devise fast compilers and CAD tools to exploit this parallelism effectively
explore and customize architecture organizations required to support parallelism and reflect changing VLSI costs
build efficient performance models of target systems to provide early feedback on parallel performance, correctness and quality
create design environments and methodologies for accelerating application development
Academic Information
Ph.D. (expected Fall 2009) California Institute of Technology, Pasadena, USA M.S. in Computer Science (2006) from California Institute of Technology, Pasadena, USA M.S. in Electrical Engineering (2005) from California Institute of Technology, Pasadena, USA B.E. in Electronics and Telecommunication (2002) from University of Pune, India (Govt. College of Engineering, Pune) 10+2 (1998) from Laxmanrao Apte Prashala, Pune, India 10 (1996) from Karnatak High School, Pune, India (now Shamrao Kalmadi High School)