- Q1: Compare and contrast the 21164's 2-level on-chip cache
hierarchy (8KB direct-mapped L1s, 96KB L2) with the 21264's single
level of on- chip caches (set-associative 64KB first-level caches).
What differences between these two processor microarchitectures might
have result in this different design decision?
- Q2: Explain the 21264's innovative use of next-line and way
prediction to provide high-bandwidth fetch. How does this scheme
interact with their advanced branch predictor? How does this improve
over the 21164's approach to high-bandwidth fetch?
- Q3: The 21264 makes heavy use of prediction and speculation. For
example, it employes advanced branch prediction to avoid branch
misprediction penalties and prefetching to reduce cache misses. List
several other examples of the 21264's use of prediction/speculation
and identify the problem each is attacking (using just a few words, as