`timescale 1ns / 1ps `define EOF 32'hFFFF_FFFF `define NEWLINE 10 `define NULL 0 module testbench_v; // Inputs reg wen; reg rst; reg clk; reg[2:0] rsel1; reg[2:0] rsel2; reg[2:0] wsel; reg[15:0] wdata; // Outputs wire[15:0] rdata1; wire[15:0] rdata2; // Instantiate the Unit Under Test (UUT) regfile8_16_2r1w myRegfile ( .rsel1(rsel1), .rsel2(rsel2), .wsel(wsel), .rdata1(rdata1), .rdata2(rdata2), .wdata(wdata), .wen(wen), .rst(rst), .clk(clk) ); integer file, char, retval; reg[15:0] expectedValue1; reg[15:0] expectedValue2; always #5 clk <= ~clk; initial begin // Initialize Inputs rsel1 = 0; rsel2 = 0; wsel = 0; wen = 0; rst = 1; wdata = 0; clk = 0; // open the test inputs file = $fopen("lab2.input.test", "r"); if (file == `NULL) $finish; // Wait 100 ns for global reset to finish #100; #5 rst = 0; char = $fgetc(file); while (char != `EOF) begin if (char == "#") // eat a comment line begin while (char != `NEWLINE) begin char = $fgetc(file); end end else begin retval = $ungetc(char, file); // push back the non-comment char #1 retval = $fscanf(file, "%b %b %b %b %d %d %d", rsel1, rsel2, wsel, wen, wdata, expectedValue1, expectedValue2); #8 //once every clock cycle if (rdata1 != expectedValue1) begin $display("Error: Value of register %b on output 1 should have been %d, but was %d instead",rsel1, expectedValue1,rdata1 ); end if (rdata2 != expectedValue2) begin $display("Error: Value of register %b on output 2 should have been %d, but was %d instead",rsel2, expectedValue2,rdata2 ); end #1 char = $fgetc(file); end end // end while $fclose(file); $finish; end endmodule