Announcements

• [Apr 4] - Superscalar skeleton files are now available.
• [Apr 4] - Lab 3 testbench is now available; updated Lab 3 description.
• [Mar 24] - Lab 3: Pipelined processor is now available.
• [Mar 16] - Added lectures notes on Pipelined P37x Processor.
• [Mar 2] - Added ModelSim Advanced Features Tutorial
• [Feb 25] - Added Lab 2: Non-pipelined processor
• [Feb 16] - Added Lab 2 worksheet
• [Feb 16] - Added Xilinx PROM Tutorial
• [Feb 15] - Updated Peter's lab hours.
• [Feb 8] - The CSE372 PHPbb discussion board is now available
• [Feb 6] - Added Xilinx ISE Tips
• [Jan 15] - The Introduction lecture notes are now online
• [Jan 12] - Welcome to CSE372

Office Hours

KLab schedule

The TAs are in the KLab at the following times:

• Monday: 4:30-7:30 (Andrew)
• Tuesday: 1:30-4:30 (Zheng), 4:30-7:30 (Tony), 7:00-9:00 (Peter)
• Wednesday: 1:00-3:00 (Zheng), 4:30-6:00 (Andrew)
• Thursday: 1:00-3:00 (Peter), 5:30-7:00 (Armand)
• Friday: 1:00-3:00 (Zheng), 4:30-6:30 (Armand)

Labs

• Lab 0: Getting started
• Lab 1: Combinational logic and ALUs
• Lab 2: Non-pipelined processor
• Lab 3: Pipelined processor

Lecture Notes

• Unit 0 - Introduction
• Unit 1 - Verilog
• Unit 2 - FPGAs
• Unit 3 - Design and P37x Processor
• Unit 4 - Pipelined P37x Processor
• Unit 5 - Synthesis
• Unit 6 - Wrapup

Schedule

Additional Reading Materials and Resources

CSE372 tutorials:

• Instructions for mapping your eniac drive
• Xilinx Verilog Tutorial
• ModelSim Simulation Tutorial
• ModelSim Advanced Features Tutorial
• Xilinx Built-In Self Test Tutorial
• Xilinx ISE Tips
• Xilinx PROM Tutorial

Xilinx documentation:

• Xilinx Synthesis and Verification Design Guide - information on what synthesis results to expect given HDL input code.
• Xilinx Synthesis Technology (XST) User Guide - information about Xilinx primitives and Verilog examples that will synthesis to specific structures.
• Xilinx Constraints Guide - information about various synthesis parameters and tuning.

On-line Verilog references:

• The Elements of Logic Design Style by Shing Kong, 2001.
• On-line Verilog HDL Quick Reference Guide
• Useful Verilog links

In addition, the textbook for CSE371 (Patterson and Hennessy's Computer Organization and Design) has a Verilog tutorial on the included CD. Look for it under "tutorials" and "Verilog".

There is no additional textbook required for CSE372. However, we'll be using the Verilog hardware description language (HDL), so you may wish to obtain or consult one of the following books on Verilog:

• Verilog HDL Synthesis: A Practical Primer by J. Bhasker, 1998. A approximately 200 page overview of a synthesizeable subset of Verilog.
• Advanced Digital Design with the Verilog HDL by Michael Ciletti, 2003. Verilog plus lots of digital logic design (almost 1000 pages).
• HDL Programming Fundamentals: VHDL and Verilog by Nazeih Botros, 2006. A good interleaved description of Verilog and VHDL; it has approximately 500 pages, but as both VHDL and Verilog are covered, it doesn't cover that much more than Bhasker.

Course Syllabus

Laboratory for CSE 371. In this laboratory section, students gain experience
with digital design techniques by designing and implementing actual ciruits
using Verilog HDL and FPGAs. Five assignments culminate in the design and
simulation of a complete 16-bit integer pipelined CPU.