Seminars & Meetings | Abstracts

Wednesday, October 20, 2010

Towne 337, 11a.m. - 12:00 p.m.


Linh Phan
Department of Computer & Information Science
University of Pennsylvania
Modeling Buffers with Data Refresh Semantics in Automotive Architectures

Abstract:

Automotive architectures consist of multiple electronic control units > > (ECUs) which run distributed control applications. Such ECUs are > > connected to sensors and actuators and communicate via shared > > buses. Resource arbitration at the ECUs and also in the communication > > medium, coupled with variabilities in execution requirements of tasks > > results in jitter in the signal/data streams existing in the system. As > > a result, buffers are required at the ECUs and bus > > controllers. However, these buffers often implement different > > semantics -- FIFO queuing, which is the most straightforward buffering > > scheme, and data refreshing, where stale data is overwritten by > > freshly sampled data. Traditional timing and schedulability analysis > > that are used to compute, e.g., end-to-end delays, in such automotive > > architectures can only model FIFO buffering. As a result, they return > > pessimistic delay and resource estimates because in reality > > overwritten data items do not get processed by the system. In this > > paper we propose an analytical framework for accurately modeling such > > data refresh semantics. Our model exploits a novel feedback control > > mechanism and is purely functional in nature. As a result, it is > > scalable and does not involve any explicit state modeling. Using this > > model we can estimate various timing and performance metrics for > > automotive ECU networks consisting of buffers implementing different > > data handling semantics. We illustrate the utility of this model > > through three case studies from the automotive electronics domain.