The multi-core era is irreversibly here. The transition from single-core to few cores has been relatively smooth. However, the unending need for higher performance will bring processors with hundreds and thousands of cores in the market pretty soon. But what are the implications of this to engineering, and software industry in general and computer science in particular? How is industry embracing this change? Are we ready? One of the challenges that we have been working on is the absence of memory virtualization in many-core architectures. Caches were the most important pillar of computer architecture in the single-core era. Caches provided the illusion of a single large unified memory, and kept programming simple and same. However, caches do not scale well with number of cores, and also consumes a lot of power. Therefore to improve the power-efficiency, and enable large number of cores in a processor, computer architects are in search of alternative memory hierarchies. Limited Local Memory multi-core architecture is a scalable memory design in which each core has access to only its small local memory, and explicit DMA instructions have to be inserted in the program to transfer data between memories. The IBM Cell processor, which is in the Sony Playstation 3 is a popular example of this architecture. The roadrunner supercomputer, which broke the peta-scale computation record is one of the most power-efficient super-computers, and is made of IBM Cell processors. Such high power-efficiency comes partly at the cost of simplicity of programming. Programming LLM architecture is not simple, as it requires application change. Application developers have to be cognizant of the small size of the local memory, and have to insert instructions to perform this data transfer between the memories. My talk will summarize our efforts at automating this memory management.
Aviral Shrivastava is Assistant Professor in the School of Computing Informatics and Decision Systems Engineering at the Arizona State University, where he has established and heads the Compiler and Microarchitecture Labs (CML). He received his Ph.D. and Masters in Information and Computer Science from University of California, Irvine, and bachelors in Computer Science and Engineering from Indian Institute of Technology, Delhi. He is a 2011 NSF CAREER Award Recipient and is credited for over $1.5 million of research. His research lies at the intersection of compilers and architectures of embedded and multi-core systems, with the goal of improving power, performance, temperature, energy, reliability and robustness. His research is funded by NSF and several industries including Intel, Nvidia, Microsoft, Raytheon Missile Systems etc. He serves on organizing and program committees of several premier embedded system conferences, including ISLPED, CODES+ISSS, CASES and LCTES, and regularly serves on NSF and DOE review panels.