CS294-7: Reconfigurable Computing
Control Number: #24929
Units: 3
Term: Spring 1997
Time: TR 9:30-11AM
Place: Soda 505 (n.b. change from scheduled location)
Instructors: Dr. André DeHon and Prof. John Wawrzynek
Administrative Assistant: Tim Ryan
Description
The emergence of high capacity reconfigurable devices is igniting a
revolution in general-purpose processing. It is now becoming possible to
tailor and dedicate functional units and interconnect to take advantage of
application dependent dataflow. Furthermore, machines have been proposed
that dynamically change their configuration with changing data sets and
algorithm needs. Early research in this area of reconfigurable
computing has shown encouraging results in a number of spot areas
including cryptography, signal processing, and searching -- achieving
10-100x computational density over more conventional processor solutions.
In this class we attempt to pull together the basic foundations of
reconfigurable computing, sort out where it is interesting, and understand
both how to architect reconfigurable systems and how to apply them to
solving challenging computational problems. We will revisit basic
questions about what building blocks we need in order to compute and
rethink how we build computing systems based on today's technology costs.
For more motivation and background, see André's presentation on
``The Role of Configurable Computing'' and viewpoint article on
``Directions in General-Purpose Computing Architectures''.
Student Requirements
Students will be required to attend class, read research papers,
scribe notes from a couple of lectures, and complete two individual
mini-projects -- one aimed to familiarize the student with mapping an
application to a reconfigurable device and one oriented to address
an interesting research question.
Topics Planned
- History: RC systems, programmable devices
- VLSI Costs and Constraints: costs, area, power, scaling
- Spatial Computational Styles: systolic architectures and
algorithms, cellular automata
- Architecture:
- Basics: instructions, compute blocks, interconnect,
retiming (memory)
- Reusing/sharing: folding/sharing, serialization,
swapping
(includes: coupled architecture, multicontext, partial
configuration, and run-time reconfiguration)
- Dynamic requirements: data-driven flow and hardware
requirements, uncommon case handling, dynamic and late-binding
specialization
- Programming and Mapping:
- High-level (``How do we program these systems''):
e.g. dataflow extraction from serial programs, behavioral
specification, SDF, libraries, hardware/software codesign
- Middle-ware/Transformation/Optimization: retiming, allocation, binding
- Back-end Mapping: logic, LUT, and datapath mapping,
partition, place, and route
- Defect Tolerance: yield model, sampling and sparing, costs
and benefits
- Power: low-power analysis, circuit and system level
techniques for power reduction
(links to handouts and lecture-by-lecture reading provided in calendar)