Computer Science 294-7 Lecture #18
Compute Blocks

Notes by Nathan Slingerland

I. Look Up Tables (LUT's)

Look up tables (LUTs) - perform a function (translation) from a set of input bits to output bit(s)

A K-LUT is a look up table with K input lines

As discussed in Hastings and Reddy paper, look up tables can be used to quickly perform sophisticated computational functions (color transform, texture mapping, encryption function, character translation, etc.)

How much computation can be performed by table lookup?





Note: For lower bound note interested in the trivial absolute lower bound of an identity function



Why use 4-LUTs? See Part III - Characterizing LUT Design Parameters

 

II. Comparing Memories and Programmable Arrays of 4-LUTs

Memories have less interconnect overhead, but silicon area used can not be precisely customized according to the complexity (degree of structure) of the computational task to be performed (memory size a power of two according to number of address lines; entire memory must be used)

Programmable interconnect of a 4-LUT array (e.g. Xilinx CLBs) can be used to exploit any inherent structure in a function

LUT area < interconnect area. However, complexity of most functions << 2^M

Example:

Device	Silicon Resource	Delay Parameter
32Kx8 SRAM	170M lambda2	21 ns latency
XC3042 (288 4-LUT Array)	180M lambda2	13 ns CLB delay


15-bit Parity Calculation: 5 4-LUTs (<2% XC4032) or 3.125M lambda ²
Entire SRAM (170M lambda²)

7-bit Add: 14 4-LUTs (<5% XC4032) or 8.75M lambda²)
Entire SRAM (170M lambda²)





III. Characterizing LUT Design Parameters

Francis and Rose paper

K: # inputs to LUT

 

K-input LUTs Needed to Implement Benchmark Functions


K-input LUT Area

Empirical observation (correlated to statistical models): Routing area roughly linear in K

See Fig. 4.8, Rose paper for detailed picture of why 4-LUT minimizes area



Composite: Total LUT Area vs. K

Number of LUTs decreasing with increasing K, but LUT area increasing



Rate of LUT count decrease slowing as K increases while the rate of area growth increasing (exponential term for LUT programming)
Therefore, we should expect to find a minimum point



K-input LUT Delay

For small LUTs:



LUT Delay v/s K



Delay depends on function complexity (and therefore circuit depth)




Circuit depth v/s K



Total Delay

Total delay - product of the LUT+interconnect delay and the "Rose Average" circuit depth above.
(These are not the simple/most complex bounds discussed above.)



IV. Summary

Memory offers the best functional density for very complex functions, but scales poorly for structured tasks

Most tasks have structure, which can be exploited by LUT arrays with programmable interconnect (FPGA's)

LUT area minimized for K=4 (i.e. Xilinx)

LUT delay minimized for K=5..6

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