The first project was aimed primarily at giving students experience building implementing computations spatially as well as giving them experience designing/using FPGAs in a traditional design flow.
See the project assignment for further details on the assignment.
| Student | Project | Highlights |
|---|---|---|
| Eylon Caspi | FP Adder | 36MFLOP, pipelined 16b FP Add/Sub |
| Luca Carloni | Motion Search | 20+MHz systolic matching |
| Philip Chong | DES Cyrptanalysis | 900K keys/s, 300CLBs |
| Brent Chun | Priority Queue | 40MHz clock, 4b, 12CLBs/PE |
| Varghese George | Correlator | 64MHz front-end operation, compare to custom |
| Randy Huang | Division | 5.3MHz, 570ns, 16.8b by 24.0b division, 669 CLBs, compare std. cell |
| Christoforos Kozyrakis | Square Root | 5 microsecond operation, 122 CLB (sans final multiply) |
| Adrian J. Isles | Priority Queue | 24MHz clock, 4b data, ~25 CLBs/PE |
| Bruce McGaughy | Binary to BCD | 85MHz pipelined in 114 CLBs |
| Amit Mehrotra | Systolic GCD | bit pipelined for 50MHz operation (3x speed of published result) |
| Roy A Sutton | 3x3 convolution | PADDI-II design |
| Nathan Slingerland | Sorting | 25MHz, 16b key, 34 CLBs/sort PE |
| William Tsu | Division | ?? latency, 25 CLB for 4b design |
| Nicholas Weaver | Specialized Sequence Match | 100MHz, 4 CLB/PE (compare 28 CLBs, 12MHz unspecialized) |
| Charlie Repetti | Audio Stream Filtering | |
| James Young | Priority Queue | 33MHz, 8b, 16 CLBs/PE |