Final Project -- CS294-7: Reconfigurable Computing

The second project was a much more open project intended to give students a chance to dig further into some research area and demonstrate mastery of the course material.

See the project assignment for further details on the assignment.

Student Project Highlights

Eylon Caspi GARP Placement Optimization Shows that GaMa synthesis is well matched to Garp resources. Identifies some potential opportunities to reduce the latency of GaMa mapped designs.

Luca Carloni FPGA Interconnect Requirements Suggests interconnect requirements don't vary widely for designs with 100's of LUTs.

Philip Chong Fast FPGA Compilation Suggests that GaMa mapping to Xilinx provides fast placement with no area or delay penalty.

Brent Chun Application Tracing for Functional Unit Specialization Early estimates of bit usage in programs; points at large potential opportunity to restrict datapath sizes.

Varghese George Power Optimized FPGA Arch. Formulates a different logic block growth model for adder dominated designs and shows a 5-input 3-output (4 3-LUTs) consumes least power for an adder rich benchmark set.

Randy Huang Sea-of-Gates FPGA Shows some marginal advantage to non-dense placement in symmetric FPGA model.

Christoforos Kozyrakis LUT Input Switch Implementation Demonstrates advantage of depopulated N choose K switching scheme and encoded configurations. Also compares SRAM/DRAM implementations.

Bruce McGaughy Time-Area Relationships for FPGA Library Functions Shows 4b adder (nibble-serial) and 8b multiplier (byte-serial) units are the sweet spot in Xilinx throughput density curve (using unpipelined fast carry support)

Nathan Slingerland Reconfigurable Array Specialization in Media Processing Shows the area-time advantages of select specialized datapaths as compared to a generic datapath for media-oriented computations.

Roy Sutton A Method for Interconnect Switch Evaluation of Clustered Multiprocessor Systems Demonstrates one way to categorize switching capabilities within a cluster of processing elements.

William Tsu Universal Switch Box v/s Xilinx Implementations Shows density of universal switch layout is comparable to diamond switch (used by Xilinx). Also shows domains where switches and wires dominate for symmetric FPGA, 4-sided switchboxes.

Nick Weaver Generator Prototype Shows generators can synthesize designs in seconds; highlights design requirements for a generator language.

James Young Java support for developing Partitioners Highlights useful monitors for progress during partitioning and some typical characteristics of partitioning algorithms.

Student	Project	Highlights
Eylon Caspi	GARP Placement Optimization	Shows that GaMa synthesis is well matched to Garp resources. Identifies some potential opportunities to reduce the latency of GaMa mapped designs.
Luca Carloni	FPGA Interconnect Requirements	Suggests interconnect requirements don't vary widely for designs with 100's of LUTs.
Philip Chong	Fast FPGA Compilation	Suggests that GaMa mapping to Xilinx provides fast placement with no area or delay penalty.
Brent Chun	Application Tracing for Functional Unit Specialization	Early estimates of bit usage in programs; points at large potential opportunity to restrict datapath sizes.
Varghese George	Power Optimized FPGA Arch.	Formulates a different logic block growth model for adder dominated designs and shows a 5-input 3-output (4 3-LUTs) consumes least power for an adder rich benchmark set.
Randy Huang	Sea-of-Gates FPGA	Shows some marginal advantage to non-dense placement in symmetric FPGA model.
Christoforos Kozyrakis	LUT Input Switch Implementation	Demonstrates advantage of depopulated N choose K switching scheme and encoded configurations. Also compares SRAM/DRAM implementations.
Bruce McGaughy	Time-Area Relationships for FPGA Library Functions	Shows 4b adder (nibble-serial) and 8b multiplier (byte-serial) units are the sweet spot in Xilinx throughput density curve (using unpipelined fast carry support)
Nathan Slingerland	Reconfigurable Array Specialization in Media Processing	Shows the area-time advantages of select specialized datapaths as compared to a generic datapath for media-oriented computations.
Roy Sutton	A Method for Interconnect Switch Evaluation of Clustered Multiprocessor Systems	Demonstrates one way to categorize switching capabilities within a cluster of processing elements.
William Tsu	Universal Switch Box v/s Xilinx Implementations	Shows density of universal switch layout is comparable to diamond switch (used by Xilinx). Also shows domains where switches and wires dominate for symmetric FPGA, 4-sided switchboxes.
Nick Weaver	Generator Prototype	Shows generators can synthesize designs in seconds; highlights design requirements for a generator language.
James Young	Java support for developing Partitioners	Highlights useful monitors for progress during partitioning and some typical characteristics of partitioning algorithms.

CS294-7: Reconfigurable Computing