Final Project Report Schedule

Location: SODA 505 (including Tuesday afternoon)

Day Time Student Project
Tuesday, May 6th 9:40am Roy Sutton A Method for Interconnect Switch Evaluation of Clustered Multiprocessor Systems
9:55am Brent Chun Application Tracing for Functional Unit Specialization
10:10am Bruce McGaughy Time-Area Relationships for FPGA Library Functions
10:25am Break
10:30am William Tsu Universal Switch Box v/s Xilinx Implementations
10:45am Philip Chong Fast FPGA Compilation
Tuesday, May 6th (also in Soda 505) 5:10pm Randy Huang Sea-of-Gates FPGA
5:25pm Christoforos Kozyrakis LUT Input Switch Implementation
5:40pm Break
5:45pm James Young Java support for developing Partitioners
Thursday, May 8th 9:40am Varghese George Power Optimized FPGA Arch.
9:55am Eylon Caspi GARP Placement Optimization
10:10am Luca Carloni FPGA Interconnect Requirements
10:25am Break
10:30am Nick Weaver Generator Prototype
10:45am Nathan Slingerland Reconfigurable Array Specialization in Media Processing


CS294-7: Reconfigurable Computing