Reading for Tuesday, April 8

1. Nam-Sung Woo. Revisiting the Cascade Circuit in Logic Cells of Lookup Table Based FPGAs. In Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 90--96. ACM, February 1995.
2. Kevin Chung and Jonathan Rose. TEMPT: Technology Mapping for Exploration of FPGA Architectures with Hard-Wired Connections. In Proc. 29th ACM/IEEE Design Automation Conference, June 1992, Anaheim, CA, pp. 361-367.

Supplemental Reading

1. Kevin Chung, Satwant Singh, Jonathan Rose, and Paul Chow. Using Hiearchical Logic Blocks to improve the Speed of FPGAs. In FPGAs, Will Moore and Wayne Luke, eds. (proceedings of the Oxford 1991 International Workshop on Field Programmable Logic and Applications), pp. 102--113.
2. Soon Ong Seo, A High Speed Field-Programmable Gate Array Using Programmable Minitiles, University of Toronto Master's Thesis, 1994.