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Writings on Interconnect Design

How do we systematically design interconnection networks? for on-chip switching networks? as we scale to very large network sizes? Much of our work has been done in the context of switching for FPGAs, but the results and insights are broadly applicable to on-chip networks (multiple processors on a chip, Programmable Systems-on-a-Chip). FPGAs, with their fine grain size, have the challenge and advantage that they have to deal with larger networks earlier than larger grained processors. Today commercial designs have over 100,000 processing elements on a die and continued scalling pushes us to even larger networks.

André DeHon