About
I am a Ph.D. candidate in Computer & Information Science at the University of Pennsylvania, advised by Prof. Boon Thau Loo and co-advised by Prof. Mohammad Javad Amiri. I also collaborate closely with Prof. Ryan Marcus on adaptive data management and distributed learning systems.
My research focuses on adaptive distributed databases, intelligent blockchains, and machine learning for systems. I have also worked on TCP migration and infrastructure projects at UPenn and Microsoft Research.
Research Interests
My research interests span distributed systems, machine learning for systems, and Byzantine fault tolerance:
- Adaptive Distributed Databases: Developing techniques that dynamically adjust partitioning strategies and system configurations in response to changing workloads
- Machine Learning for Systems: Using reinforcement learning and other ML approaches to optimize distributed system performance
- Byzantine Fault Tolerance: Creating scalable, secure protocols for untrusted environments
Selected Publications
- Paper on Adaptive Distributed Systems Under Submission
- Towards Full Stack Adaptivity in Permissioned Blockchains VLDB '24
- Towards Adaptive Fault-Tolerant Sharded Databases AIDB @ VLDB '23
- AdaChain: A Learned Adaptive Blockchain VLDB '23
Experience
Research Assistant
2019 - Present
University of Pennsylvania
- Conducting research in adaptive distributed databases and machine learning for systems.
- Worked on TCP migration projects in collaboration with Microsoft Research.
Teaching Assistant
2020 - 2024
University of Pennsylvania
- CIS 471: Computer Architecture (Instructor: Joe Devietti)
- CIS 548: Operating Systems (Instructor: Boon Thau Loo)
Undergraduate Research Assistant
2015 - 2018
Nirma Institute of Technology
- Research in embedded systems, IoT optimization, and human action recognition using deep learning.
Research Intern
Summer 2017
RISE Lab, IIT Madras
- Worked on FPGA-based high-speed divider architectures (radix-4 SRT dividers).
Design Engineer
2018 - 2019
Bluespec Inc.
- Architected and optimized RISC-V cores with a focus on pipelining and timing closure.
- Automated deployment of hardware cores from high-level specifications
- Developed testing frameworks for hardware validation