ESE170: Principles of Digital Design

Prof: Jan Van der Spiegel

Spring 2015

Syllabus (tentative)

 No. Spring 2015 TOPIC Reading Lab Schedule (tentative; check the Lab website) Date Texts: 1.Logic and Computer Design Fundamentals, Mano and Kime (4th Edition) 2. Digital Design, Interactive Textbook by ZyBooks (free for students enrolled in the class) Textbook section 1 1/14/2015 Introduction to Digital Systems; levels of abstraction; information representation; course objectives. 1-1 No Lab 2 1/16/2015 Number systems; Conversion between number systems 1-2, 1-3 1/19/2015 Martin Luther King Jr. Day - no class No Lab 3 1/21/2015 ASCII Code; Decimal and Gray codes 1-4, 1-5, 1-6 Lab 0: Intro and Xilinx Tutorial (Half-Adder) 4 1/23/2015 Binary logic; Boolean Algebra (basic identities). 2-1, 2-2 5 1/26/2015 Standard forms 2-3, Theorems Lab 1: Full Adder 6 1/28/2015 Circuit Optimization and K-maps 2-4, 2-5 7 1/30/2015 Map manipulation (implicants), don't cares 2-5 8 2/2/2015 Other gate types, XOR gates; Hi-impedance outputs 2-8, 2-9, 2-10 Lab 2: Traffic Light Controller 9 2/4/2015 Iterative circuits, Binary Adders 4-1, 4-2 10 2/6/2015 Binary subtractor; Signed binary adder-subtractor. 4-3, 4-4 11 2/9/2015 Signed binary Addition and Subtraction 4-4, 4-5 Lab 3: Four-bit Adder 12 2/11/2014 Binary Multiplication;Design Procedure; Hierarchical Design; Tech. mapping 4-5; 3-1, 3-2, 3-3, 3-4 13 2/13/2015 Combinational Functional Block: Decoders 3-7 14 2/16/2015 Combinational Functional Block: Encoders 3-7 Lab 4: Combination Multiplier (Week 1) 15 2/18/2015 Multiplexers and Applications 3-8 16 2/20/2015 Sequential circuits; latches 5-1; 5-2 17 2/23/2015 Review Combinational Circuits Lab 4: Comb. Mult. (Week 2) Report Overview 18 2/25/2015 Midterm 1 (Combinational Logic) 19 2/27/2015 Latches (cont), Flip-flops 5-2, 5-3 20 3/2/2015 Flip-flops (cont) 5-3 Floating Week Report 1: Adder and Multiplier 21 3/4/2015 Sequential circuit analysis 5-4 22 3/6/2015 Sequential circuit analysis and review midterm 5-4 3/6-10/15 Spring Break 23 3/16/2015 Sequential circuit analysis; design 5-5 Lab 5: ALU (Week 1) 24 3/18/2015 Sequential circuit design (cont) 5-5 25 3/20/2015 Sequential circuit design: unused states and verification (timing issues in Mealy machines) 5-6 26 3/23/2015 Other flip-flop types 5-6 Lab 5: ALU (Week 2) 27 3/25/2015 State machine diagrams and constraints 5-7 28 3/27/2015 State machine diagrams - examples 5-7 29 3/30/2015 Practical Considerations (debouncing, synchronizer, metastability); delay and timing. 5-7 ; 6-2, 6-3 Lab 6: VGA Controller 30 4/1/2015 Timing in sequential circuits; Registers, Register Transfers and Micro-operations 7-6 31 4/3/2015 Shift Registers and Counters 6-4, 7-1, 7-2, 7-3 32 4/6/2015 Shift Registers and Counters (cont.) 7-5, 7-6 Lab 7: RPN Calculator Report 2: VGA Controller 33 4/8/2015 Midterm 2 (Sequential Logic) - Tentative date, check in class 34 4/10/2015 Counters (cont.) 7-6 35 4/13/2015 Register-cell design and MUX-based transfers 7-7, 7-8 Lab 8: Pong Game (Week 1) 36 4/15/2015 MUX-based and Bus-based transfers; Control of Register Transfers 7-8, 7-9, 7-10 37 4/17/2015 Control of Register Transfers (cont.) 7-10 38 4/20/2015 Tri-State Bus based transfers; serial transfers 7-8, 7-9 Lab 8: Pong Game (Week 2) Report 3: ALU & RPN Calc. 39 4/22/2015 Examples of Control of Register Transfers; micro-programmed control 7-10, 7-13 40 4/24/2015 Propagation delay, Flip-flop timing 6-2, 6-3, 6-4 41 4/27/2015 Programmable Logic Implementations 6-8 6-4 42 4/29/2015 TBD Final Examination (check with the Registrar Website for full schedule) Cumulative

Last Updated: January 10, 2015