Department of Electrical and Systems Engineering

ESE171: Principles of Digital Design Laboratory


Prof: Jan Van der Spiegel

Spring 2015


The laboratory consists of hands-on assignments which accompany the lectures of ESE170. The goal is to illustrate concepts discussed in the class and to give students the opportunity to build and test real systems.

Lab exercises make use of the Xilinx ISE toolchain, which is a powerful state-of-the-art CAD tool for designing and implementating digital systems on Field Programmable Gate Array (FPGA) boards. The ESE undergraduate lab (Frederick Ketterer Lab) is equipped with the Xilinx ISE software tools. The system consists of an integrated set of tools that allows one to capture designs with schematic entry or a Hardware Description Language (HDL), and simulate, implement and test these designs. The use of programmable logic devices takes away the tedious task of wire wrapping individual gates and allows one to concentrate on the creative part of designing the circuits.

The lab assignments will introduce you gradually to the Xilinx tools and will serve to illustrate the material covered in class. The first set of labs deal with combinational circuits and the second set introduces sequential circuits. This course uses an FPGA board from the Digilent Corporation, which has a Xilinx Virtex2P chip on-board.

Labs are done in groups of two, with group lab reports and individual prelabs (see the lab policies and Blackboard for more information).



The goals of this laboratory course are:

  1. To apply concepts and methods of digital system design techniques as discussed in the class (ESE170) through hands-on projects. [a]
  2. To analyze the results of logic and timing simulations and to use these simulation results to debug digital systems. [b]
  3. To learn to design combinational and sequential digital systems starting from a word description that performs a set of specified tasks and functions. [c]
  4. To develop skills, techniques and learn state-of-the-art engineering tools (such as VHDL, Xilinx ISE, etc.) to design, implement and test modern-day digital systems on FPGAs. [i]
  5. To write clear and concise lab reports [g]
  6. To learn by using Xilinx Foundation tools and Hardware Description Language (VHDL). [i]
  7. To understand modern CAD tools for FPGA design [j]
  8. To learn through hands-on experimentation the Xilinx tools for FPGA design as well as the basics of VHDL to design and simulate digital systems. [k]

Course Logistics

Lab Schedule

Monday: 1-4pm
Tuesday: 3-6pm
Friday: 1-4pm


Jan Van der Spiegel
Office: Moore 201 (inside ESE Office)
Phone: 215-898-7116
Email: jan AT seas DOT upenn DOT edu

Teaching Assistants

General Policies

See Blackboard for more course information

Last Updated: January 4, 2015