Circuit-Level Modeling, Design, and Optimization for Digital Systems

Course: ESE370

Units: 1.0 CU
Term: Fall 2020
When: MWF 12-1pm EDT (note this will change to EST on Nov. 1)
Where: Zoom, see Piazza for link
Instructor: Tania Khanna (Levine 262, seas: taniak) (office hours: W 1-3pm, F 9-10am EDT or by appointment, see Piazza for link)
TA: Raul Leclair (seas: rleclair) (office hours: Th 10-11am, F 1-3pm, see Piazza for link)
TA: Zoe Nelson (seas: znelson) (office hours: M 8-10am, Th 2-3pm, see Piazza for link)

Prerequisites: ESE 150, ESE 215, CIS 240 is also highly recommended. Roundup of topics you should be familiar with.
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Quick Links: [Course Objectives] [Grading] [Policies] [Fall 2020 Calendar] [Reading] [Student Advice] [Piazza] [Tool Guides]

Catalog Level Description: Circuit-level design and modeling of gates, storage, and interconnect. Emphasis on understanding physical aspects which drive energy, delay, area, and noise in digital circuits. Impact of physical effects on design and achievable performance.

Role and Objectives

The goal of this course is to teach students what they need to know about the physical aspects (area, delay, energy, noise) of electronic circuits to support high-speed, low-energy, area-efficient design of robust digital and computer systems. Students will learn: This course comes after a basic introduction to devices and circuits (ESE215) and a course on gate-level digital design (ESE150/CIS240). It should serve both students who will go on to do circuit-level design and those who will work primarily at higher levels and need to be able to reason about technology and fundamental limits to establish capabilities and understand the circuit-level impact of optimizations they perform at higher levels of design. This will be the most detailed class on physical issues required for CMPE BSE students. Students may choose to continue with more advanced circuit and VLSI courses (e.g., ESE570).

Rough Syllabus (by weeks)

  1. Review transistor, introduce MOS model
  2. Gates and restoration, basic gate delay, review transient response
  3. MOS Transistors (models with physical device parameters (W,L,Na...)), scaling, variation
  4. Energy, Delay, Area implications and tradeoffs for MOS circuits
  5. Clocking, latches, flip-flops (setup, hold, clock skew)
  6. Other gate models (ratioed, pre/post-charge)
  7. RC Wire delay and Elmore delay (fanout, transistor sizing)
  8. Wire Effects (buffering, capacitive coupling/crosstalk)
  9. RAM design
  10. Noise: inductive coupling, ground bounce, ionizing particles, thermal noise
  11. Transmission lines
  12. High speed chip-to-chip signaling
  13. Energy and entropy

See Fall 2020 course calendar for day-by-day calendar with assignments.


Software Tool Guides

This course requires the use of Electric schematic capture and ngspice. Both program can be installed and run locally on your personal computer (recommended) or run remotely on eniac. Below are guides to aid you in these tools which will be introduced to you through your weekly assignments.


Grading is based on weekly assignments, exams, and projects. Projects: Three two-week simulation/design/optimization projects: (1) transistor simulation and test for logic/gates (2) transistor design and optimization for static logic/gates and (3) design and optimization of dynamic digital design.



Lectures will be held virtually via Zoom synchronously to our assigned time by the registrar (Note that this time will adjust for Daylight Savings Time). The lectures will be recorded and posted in Canvas for student use. Each lecture will be accompanied by a preclass/inclass worksheet that will be posted by 9am the day of lecture. This worksheet will be referred to in class and students will be asked to engage with it during lecture.

To facilitate access for all class members, these sessions, including your participation, are being recorded and the recordings will be made available to the class, for the duration of this course. These recordings, as well as previously recorded lectures and other course materials, are made available solely for your personal, educational use and may not be shared, copied or redistributed without the permission of Penn and the instructor. You are also not allowed to record class sessions yourselves. Unauthorized sharing or recording is a violation of the Code of Academic Integrity.

Course Announcements and Discussion

You should enroll in Piazza and it will be a closed class (I.e only those registered for the class can access it). You can find the link above and in Canvas. Piazza will be used for all course announcements and discussions.

Assignment Turnin

Homework will be due on Wednesdays (and some Mondays on select weeks) at midnight that day. Assignments must be turned in online via Canvas. Hand written assignments will be accepted, but when specified computer generated figures, graphs and results must be submitted. Homeworks must be legible and all work should be shown. Illegible submissions will not be graded. No handwritten work will be accepted or graded on projects.

Late Assignments

All students will receive a total of 4 late days they can use on homework and projects. Assignments turned within 24 hours after the due date is counted as 1 day, within 48 hours is counted as 2 days, and so on. Multiple late days can be used on assignments, but a max of one late day can be used on any projects or project milestones.

If a student turns in a late assignment without enough late days, the assignment will not be accepted and will receive a 0. It is the students' responsiblity to keep track of their late days. For extenuating circumstances, contact the instructor prior to the due date.

If assignments or exams fall due on a religious holiday, please make arrangements with the instructor to accommodate before the posted due date.


Use the Penn Course Absence Report (CAR) in Penn-in-Touch to report absences.

Grade Adjustment

Regrade requests must be submitted to the TA no later than 1 week after the assignment is returned (or grades are posted) to the students. A cover sheet detailing the discrepency should be attached to the original homework, and the TA reserves the right to regrade the entire assignment. Students are responsible for checking posted grades in a timely manner.

There are no regrades on final exams and final projects.


You may help each other understand how to use the CETS computers and course CAD tools.

Each student is expected to do his/her own work -- including developing the details, drawing circuits, performing simulations, and writing the solutions. For the homeworks and projects, you are free to discuss basic strategies and approaches with your fellow classmates or others, but detail designs, implementations, analysis, and writeups should always be the work of the individual. If you get advice or insights from others that influenced your work in any way, please acknowledge this in your writeups.

In general, you are expected to abide by Penn's Code of Academic Integrity. If there is any uncertainty, please ask.

Student Advice

Q: As a current or former student that did very well in ESE 370, what advice do you have for future students to be successful in ESE 370?

"The most important thing for me was to attend lecture, the course moves rather quickly and builds on your previous knowledge so it's key for you to attend. Additionally, Professor Khanna will send you a sheet before each lecture and completing it and writing notes on it was very helpful! I think that there was not a single lecture that I did not ask a question, so if you have doubts about something ask or come to office hours. Also, make sure you start early on the projects so you can get a good idea of what you have to do and can start planning how to do it. ESE 370 is a really interesting class and while difficult, if you attend lectures and do your best to understand the material you will do great and learn a lot!"
-Raul Leclair, Student Fall 2019, TA Fall 2020

"ESE 370 is a class that moves quickly. It will introduce you to many new topics and ask for a deeper understanding of them than you are likely used to. I found that one of the best ways to stay abreast of the material was to engage with it as it is introduced-- that means ask questions and engage in conversation in class (or in office hours) regularly, not only right before the exam as a last-minute effort to memorize the material. As for the projects and assignments, I highly recommend students practice good clean, modular design. The payoff in investing the time to do it tidily in the beginning is worth it; it will help you debug mistakes, understand the material better, and develop the design much more easily. Good luck, and enjoy!"
-Celine Lee, 370 Student Fall 2018

"ESE 370 is a very rewarding class, but not an easy class. The biggest advice I can offer is to stay on top of the work. The opened ended implementation that comes with the design problems can be a challenge. Take time to look at the assignments when they are released. This will give you sometime to think of multiple ways to solve the problems. If you wait until the last day to open assignments, you will be rushed. You may implement a working solution, but it may be over complicated and take more time than if you thought about the problem beforehand.

Also, use a mouse when working in electric (the schematic software) in order to reduce the frustration."
-AJ Geers, Student Fall 2018, TA Fall 2019

"ESE370 and its projects will give you a taste of electronics design that will be both very challenging and rewarding, and quite unique compared to other classes at Penn. To get the most out of this class and its projects, keep the following tips in mind.

1. Start early. The projects will involve many rounds of design/optimization and simulation/verification, and the simulations will eat up your time very quickly. But for engineers dealing with physical phenomena, simulations are still much faster, cheaper, and easier to test than building the physical device.

2. Be extremely disciplined in keeping your circuits organized. Design and test in modules before putting them together. Hunting down a careless error in hardware design can be significantly harder than in software because analog hardware errors can bleed across multiple components.

3. Get comfortable with reading and debugging the spice files produced by Electric. Often a wire will look connected in the Electric GUI when it isn't and that can be the source of many mysterious bugs. The spice files are the ultimate design that gets simulated by Ngspice. Spice files are also text files that can be managed by Git if you have prior experience with version control from other classes.

Electronics design may be very different from other projects you have experienced. However, the focus and discipline involved is widely applicable to many other engineering fields. Good luck!"
-Martin Deng, Student Fall 2015, TA Fall 2016, 2017

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