System-on-a-Chip Architecture

Course: ESE532

Units: 1.0 CU
Terms: Fall 2020
When: MW 10:30am--12:00pm (First Lecture W 9/2/2020)
Where: Zoom
Instructor: DeHon (office hours T4:15pm-5:30pm, Zoom)
TA: Syed Ahmed
Office Hours: TBD Zoom
TBD Zoom

Undergraduate CIS240, ESE350, (CIS371 helpful)
Graduateworking knowledge of C

URL: <>

Quick Links: [Covid-19 Fall 2020] [Course Objectives] [Project] [Grading] [Syllabus (to-be-updated)] [Course Policies] [Previous Offerings] [Documentation] [piazza] [Relation to other courses]

Catalog Level Description:

Motivation, design, programming, optimization, and use of modern System-on-a-Chip (SoC) architectures. Hands-on coverage of the breadth of computer engineering within the context of SoC platforms from gates to application software, including on-chip memories and communication networks, I/O interfacing, RTL design of accelerators, processors, concurrency, firmware and OS/infrastructure software. Formulating parallel decompositions, hardware and software solutions, hardware/software tradeoffs, and hardware/software codesign. Attention to real-time requirements.

Covid-19 Fall 2020

Fall 2020 offering will plan to accommodate the ongoing Covid-19 challenge which includes, students that cannot be physically present on campus at Penn (due to travel restrictions, housing restrictions, and personal safety concerns) and the need for social distancing even for those that are on campus. Our plan will evolve with restrictions and guidance from the University. Our current plan includes: See the Provosts Covid-19 Academic Information and Resources for further University-wide information and guidance.

Course Objectives

By the end of the course, you will be able to:


Architectural building blocks and heterogeneous architecture, Hardware-Software Codesign, Embedded Software, Interfacing, Computational requirements and system analysis, Concurrency, Real Time, Design-space formulation and exploration, Costs and metrics (energy, area, runtime, reliability, predictability), Quantitative design and analysis.

Rough Syllabus Plan

  1. Overview, scope, methodology
  2. Metrics and bottlenecks
  3. Memory
  4. Computational models
  5. Data parallel microarchitectures (SIMD, Vector, GPU)
  6. Thread-level Parallelism and virtualization
  7. Real-time, reactive
  8. Spatial computations, basic mapping from high-level
  9. Fine-grained parallelism microarchitectures (FSMD, VLIW)
  10. High-level synthesis (C-to-gates, resource selection and provisioning)
  11. Verfication
  12. On-chip networking / Network-on-Chip
  13. VLSI technology and scaling
  14. Defect and fault tolerance

Detailed Fall 2020 schedule coming soon, but you can consult the 2019 Syllabus for reference until then.


This course will include a substantial project running throughout term. Students work in groups of 2. Platform will be an SoC-FPGA (e.g., Xilinx Zynq or Intel/Altera Arria), allowing the provisioning of soft-core processors, accelerators, and memory in addition to the use of the embedded SoC logic. It will start with a significant task (like video acquisition, processing, compression, networking). Course starts by running the task on single processor and identifying resource requirements. Then, it will deal with I/O for task. It then migrates the task to multiple processors to accelerate. After that, it develops custom accelerators for task and integrate with networked processor. The final half of the course is an open-ended optimization project using the techniques and design options introduced in the course.


Grading is based on:



Writeups must be done in electronic form and submitted through Canvas (below). Use CAD or drawing tools where appropriate. Handwritten assignments and hand-drawn figures are not acceptable.

The specific homework assignments will specify what portion of the writeup can be performed jointly and what part should be individual.

See the course Writeup Guidlines for full details.

Portions of the project milestones and final will be per group. Look for specific instructions associated with the project.

Homework Turnin

All assignments will be turned in electronically through the Penn Canvas website. Log in to canvas with your PennKey and password, then select ESE 532 from the Courses and Groups dropdown menu. Select Assignments from the links on the left and select the assignment you wish to submit for. Submission should be as a single file (preferably .pdf).

Late Assignments

Assignments must be turned in by the published due date to receive credit.

We will grant each student 3 free late days for the course of the entire term (homework and project milestones) for individual turn-in assignments or assignment components. That means you could, for example, turn in three assignments one day late each or one assignment 3 days late and still receive full credit. The quantum for free late days is a day, so you cannot turn in every assignment 6 hours late and receive full credit. There are no free late days for group turn-ins.


Students are allowed and encouraged to help each other with the Xilinx tools (SDSoC, SDK, Vivado, Vivado HLS, Windows, Linux) used for the course, but are disallowed from developing collaborative design solutions (C-code, pragmas, design and analysis) outside of identified project groups. Each team must develop its own design solution; collaborating across teams is a violation of the collaboration policy. Within a project group, the assignment will specify what part should be done as a group and what part should be done individually.

In general, you are expected to abide by Penn's Code of Academic Integrity. If there is any uncertainty, please ask.


Use the Penn Course Absence Report (CAR) in Penn-in-Touch to report absences.

Preclass Worksheets

Preclass worksheets will be available for a period of time before the lecture and at least 24 hours after the lecture. After that, we do not promise they are available. You are responsible for keeping up with the course as it happens, collecting them, and keeping them to use for review.

Previous Offerings

Comparison to ESE534

This course inherited less than 25% of the material from the
last offering of ESE534. This course does not go deep into how to design a spatial substrate (compute, interconnect), nor go deep into processor--FPGA continuum and instruction design. If offered again (no current plans), ESE534 would likely evolve to take this course as a pre-requisite. Possibly ESE534 and 535 will merge into a single advanced, follow-on course. Note that ESE534 did not have the kind of hands-on project that becomes a key component of this course.

Comparison to CIS501

This course is complementary to CIS501. This course is more focused on custom, application-oriented design with real-time concerns, while CIS501 focuses on ISA compatibility and best-effort designs. This course assumes you are willing to recompile and, typically, rewrite your application code; as a result, it does not touch upon the ISA abstraction and compatibility and will have almost nothing on dynamic ILP and pipelining of a general-purpose processor. This course will be driven more by real-time concerns rather than best-effort tasks, whereas CIS501 is more focused on best-effort. This course will spend one day on the high-level benefits of memory hierarchy, but will not dive deep into automatically hardware-managed cache-design and cache-hierarchies, which is a major component of CIS501. This course will mostly look at non-shared memory models and architectures with, at most, a small nod to the existence and challenges in shared memory, whereas CIS501 is mostly focused on shared-memory models and architectures.
Last modified: Fri Jul 3 11:42:48 EDT 2020