Digital Integrated Circuits AND VLSI Fundamentals

Course: ESE570

Catalog Level Description: The course explores the design aspects involved in the realization of CMOS integrated circuits/systems from device up to the register/subsystem level. It addresses major design methodologies with emphasis placed on structured full custom design. The course includes the study of the MOS device, critical interconnect and gate characteristics that determine the performance of VLSI circuits. It also includes CMOS logic design from transistor level schematic to layout for fabrication. Students will use state-of-the art CAD tools to verify designs and develop efficient circuit layouts.

• Apply principles of hierarchical digital CMOS VLSI, from the transistor up to the system level, to the understanding of CMOS circuits and systems that are suitable for CMOS fabrication.
• Apply the models for state-of-the-art VLSI components, fabrication steps, hierarchical design flow and semiconductor business economics to judge the manufacturability of a design and assess its manufacturing costs.
• Design simulated experiments using Cadence to verify the integrity of a CMOS circuit and its layout.
• Design digital circuits that are manufacturable in CMOS.
• Apply the Cadence VLSI CAD tool suite layout digital circuits for CMOS fabrication and verify said circuits with layout paarasitic elements.
• Apply their course knowledge and the Cadence VLSI CAD tools in two design projects that involve much the same design flow they would encounter in a semiconductor design industrial setting. Projects are presented in formal reports and submission of CAD libraries for verification.

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  Rough Syllabus (by weeks)

  1. Introduction
  2. MOS Fabrication
  3. MOS Transistor Theory and Models
  4. MOS Models and IV characteristics
  5. MOS Inverters: Static Characteristics and Performance
  6. MOS Inverters: Dynamic Characteristics and Performance
  7. Combinational Logic Types (CMOS, Ratioed, Pass) and Performance
  8. Sequential Logic
  9. Dynamic Logic
  10. VLSI design and Scaling
  11. Memory Design
  12. I/O Circuits and Inductive Noise
  13. CLK Generation
  14. Robust VLSI Design for Variation

  See Fall 2021 course calendar for day-by-day calendar with assignments.

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  Main Text

  • Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. Digital Integrated Circuits, A Design Perspective, 2nd edition, Prentice Hall, 2003.
  • Errata for text
  
  
  

  Reference Texts

  • Sung-Mo (Steve) Kang, Yusuf Leblebici, and Chul Woo Kim. CMOS Digital Integrated Circuits Analysis & Design, 4th edition, McGraw Hill, 2014
    
    
  • Neil Weste, David Harris. CMOS VLSI Design: A Circuits and Systems Perspective, 4th edition, Pearson, 2011.

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  Grading

  Grading is based on homework assignments, midterm, and projects.
  • Homework Assignments [25%]
  • Project 1 [20%]
  • Project 2 [30%]
  • Midterm [25%]

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  Policies

  Lecture Mask Policy

  Masks are required to attend lecture in person, and all students are responsible for bringing their own masks. Surgical masks and Penn cloth masks are recommended. Any student coming to class without a mask will be asked to leave and reported to the Office of Student Conduct (OSC).

  Lectures

  Lectures will be held in person and will be recorded and posted in Canvas for student use.

  To facilitate access for all class members, these sessions, including your participation, are being recorded and the recordings will be made available to the class, for the duration of this course. These recordings, as well as previously recorded lectures and other course materials, are made available solely for your personal, educational use and may not be shared, copied or redistributed without the permission of Penn and the instructor. You are also not allowed to record class sessions yourselves. Unauthorized sharing or recording is a violation of the Code of Academic Integrity.

  Course Announcements and Discussion

  You should enroll in Piazza and it will be a closed class (I.e only those registered for the class can access it). You can find the link above and in Canvas. Piazza will be used for all course announcements and discussions.

  Assignment Turnin

  Homework writeups will be due on select days indicated on the course calendar at midnight and must be uploaded into Canvas as a single PDF. Handwritten assignments will be accepted, but when specified computer generated figures, graphs and results must be submitted and everything should be still combined into a single PDF and submitted in Canvas. Homeworks must be legible and all work should be shown. Illegible submissions will not be graded. No handwritten work will be accepted or graded on projects.

  Late Assignments

  All students will receive a total of 4 late days they can use on homework and projects. Assignments turned within 24 hours after the due date is counted as 1 day, within 48 hours is counted as 2 days, and so on. Multiple late days can be used on assignments, but a max of one late day can be used on any projects or project milestones.

  If a student turns in a late assignment without enough late days, the assignment will not be accepted and will receive a 0. It is the students' responsiblity to keep track of their late days. For extenuating circumstances, contact the instructor prior to the due date.

  If assignments or exams fall due on a religious holiday, please make arrangements with the instructor to accommodate before the posted due date.

  Absentees

  Use the Penn Course Absence Report (CAR) in Penn-in-Touch to report absences.

  Grade Adjustment

  Regrade requests must be submitted to the TA no later than 1 week after the assignment grades are released to the students. A cover sheet detailing the disrepency should be submitted with a copy of the original homework, and the TA reserves the right to regrade the entire assignment. Students are responsible for checking posted grades in a timely manner.

  There are no regrades on final exams and final projects.

  Collaboration

  You may help each other understand how to use the CETS computers and course CAD tools.

  Each student is expected to do his/her own work -- including developing the details, drawing circuits, performing simulations, and writing the solutions. For the homeworks and projects, you are free to discuss basic strategies and approaches with your fellow classmates or others, but detail designs, implementations, analysis, and writeups should always be the work of the individual. If you get advice or insights from others that influenced your work in any way, please acknowledge this in your writeups.

  In general, you are expected to abide by Penn's Code of Academic Integrity. If there is any uncertainty, please ask.

  Previous Offerings

  • Fall 2020
  • Spring 2020
  • Spring 2019
  • Spring 2018
  • Spring 2017
  • Spring 2016
  • Spring 2015

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