Catalog Level Description: The course explores the design aspects involved in the realization of CMOS integrated circuits/systems from device up to the register/subsystem level. It addresses major design methodologies with emphasis placed on structured full custom design. The course includes the study of the MOS device, critical interconnect and gate characteristics that determine the performance of VLSI circuits. It also includes CMOS logic design from transistor level schematic to layout for fabrication. Students will use state-of-the art CAD tools to verify designs and develop efficient circuit layouts.
See Fall 2020 course calendar for day-by-day calendar with assignments.
Lectures will be held virtually via Zoom synchronously to our assigned time by the registrar (Note that this time will adjust for Daylight Savings Time). The lectures will be recorded and posted in Canvas for student use.
To facilitate access for all class members, these sessions, including your participation, are being recorded and the recordings will be made available to the class, for the duration of this course. These recordings, as well as previously recorded lectures and other course materials, are made available solely for your personal, educational use and may not be shared, copied or redistributed without the permission of Penn and the instructor. You are also not allowed to record class sessions yourselves. Unauthorized sharing or recording is a violation of the Code of Academic Integrity.
You should enroll in Piazza and it will be a closed class (I.e only those registered for the class can access it). You can find the link above and in Canvas. Piazza will be used for all course announcements and discussions.
Homework writeups will be due on select days indicated on the course calendar at midnight and must be uploaded into Canvas as a single PDF. Handwritten assignments will be accepted, but when specified computer generated figures, graphs and results must be submitted and everything should be still combined into a single PDF and submitted in Canvas. Homeworks must be legible and all work should be shown. Illegible submissions will not be graded. No handwritten work will be accepted or graded on projects.
If a student turns in a late assignment without enough late days, the assignment will not be accepted and will receive a 0. It is the students' responsiblity to keep track of their late days. For extenuating circumstances, contact the instructor prior to the due date.
If assignments or exams fall due on a religious holiday, please make arrangements with the instructor to accommodate before the posted due date.
Use the Penn Course Absence Report (CAR) in Penn-in-Touch to report absences.
There are no regrades on final exams and final projects.
Each student is expected to do his/her own work -- including developing the details, drawing circuits, performing simulations, and writing the solutions. For the homeworks and projects, you are free to discuss basic strategies and approaches with your fellow classmates or others, but detail designs, implementations, analysis, and writeups should always be the work of the individual. If you get advice or insights from others that influenced your work in any way, please acknowledge this in your writeups.
In general, you are expected to abide by Penn's Code of Academic Integrity. If there is any uncertainty, please ask.