Photo of Hans Giesen

Hans Giesen

Ph.D. student

Implementation of Computation group
Electrical and Systems Engineering
University of Pennsylvania

Moore 315
200 South 33rd St.
Philadelphia, PA 19104


[1] H. Giesen, R. Rubin, B.Gojman, A. DeHon. Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays.
In Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA), February 2017. PDF icon

[2] H. Giesen, B. Gojman, R. Rubin, J. Kim, A. DeHon. Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-reconfiguration (COSMIC TRIP).
In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, (FCCM), May 2016. PDF icon

[3] C. Bachmann, M. Vidojkovic, X.C. Huang, M. Lont, Y.-H. Liu, M. Ding, B. Busze, J. Gloudemans, H. Giesen, A. Sbai, G.-J. van Schaik, N. Kiyani, K. Kanda, K. Oishi, S. Masui, K. Philips, H. de Groot. A 3.5mW 315/400MHz IEEE802.15.6/proprietary mode digitally-tunable radio SoC with integrated digital baseband and MAC processor in 40nm CMOS.
In Proceedings of the International Symposium on VLSI Circuits, (VLSI Circuits), June 2015.

[4] Y.H. Liu, C. Bachmann, X. Wang, Y. Zhang, A. Ba, B. Busze, M. Ding, P. Harpe, G.-J. van Schaik, G. Selimis, H. Giesen, J. Gloudemans, A. Sbai, L. Huang, H. Kato, G. Dolmans, K. Philips, H. de Groot. 13.2 A 3.7mW-RX 4.4mW-TX fully integrated Bluetooth Low-Energy/IEEE802.15.4/proprietary SoC with an ADPLL-based fast frequency offset compensation in 40nm CMOS.
In Proceedings of the International Symposium on Solid State Circuits, (ISSCC), February 2015.