A group of students at the Department of Electrical Engineering have designed "ENIAC(TM)-on-a-Chip", under supervision of Professor J. Van der Spiegel, in collaboration with Dr. F. Ketterer. This was done as part of Eniac's 50th Anniversary Celebration. They have integrated the whole "ENIAC" on a 7.44 by 5.29 sq. mm chip using a 0.5 micrometer CMOS technology. A clickable picture of the ENIAC(TM)-on-a-Chip is available here.
Their goal was to recreate the original ENIAC, following its architecture and basic circuit building blocks as much as possible. Vacuum tube circuits were modeled with transistors. Mechanical switches were replaced with electronic ones, which are essentially transmission gates, decoder and memory elements. The ENIAC used a base 10 number system as opposed to base 2, not because the engineers were not aware of base 2 but that it was thought that it would require more vacuum tubes. The units of the ENIAC are:
The original ENIAC was programmed by physically connecting one module to another with cables. For "ENIAC-on-a-Chip", this has been accomplished by pre-connecting every possible input and output of every module and mediating the conduction of the connections with programmable switches. These switches can be programmed by an external source, e.g. a PC, which will determine the "cables" that conduct, thus achieving the desired effect. This is the part of the project where modern circuit design ideas will be used. The generation of the data file for setting the switches will be done through the aid of a PC, complete with graphical interface that will mimic the various panels of the ENIAC. The operator will be able to make connections from one module to another, as was done 50 years ago, and the settings will be sent to "ENIAC-on-a-chip" which will then generate outputs that will be fed back to the PC to be displayed.
A small test chip (picture of the layout and the packaged chip) containing two main modules: accumulator and the cycling unit, as well as other supporting circuits, was fabricated in the Fall of 1995. The design of the full chip has been finalized and consists of the whole of the ENIAC, namely, 20 accumulators, the cycling and initiation units, master programmer, the high speed multiplier, divider, square rooter, constant transmitter, and function tables. The chip measures about 5x8 sq. mm. in a 0.5 micron triple metal CMOS technology.
The full ENIAC(TM)-on-a-Chip has been fabricated in a 0.5 micron, triple metal, nwell CMOS process. The chip has a size of 7.44mm by 5.29mm and contains about 174,569 transistors.
The ENIAC-on-a-Chip team consisted of Lin Ping Ang, Titi Alailima, James Tau, D. J. Yoon, Raymond Tong, Mike Feng as chip designers, Wallace Wong (Verilog Simulations), Francis Chew (DRC), Benjamin Santos, Materson Zeno (help with vacuum tube circuits) and Debra Seider (Graphical Interface).
Paper: "The ENIAC - History, Operation and Reconstruction in VLSI", J. Van der Spiegel, J. Tau, T. Alailima and L.P. Ang in The First Computers--History and Architectures, MIT Press, eds. R. Rojas, 2000.
|Picture of Eniac Chip Layout (148MByte )and packaged chip photograph|
Van der Spiegel's homepage
Jan Van der Spiegel <jan_at_seas.upenn.edu>
Created by Jan Van der Spiegel: June 9, 1995; Updated: December 27, 2012